linux-dev/drivers/soc/sifive, branch master

soc: sifive: ccache: define the macro for the register shifts

2022-10-13T18:06:55Z

Define the macro for the register shifts, it could make the code be more readable Signed-off-by: Zong Li Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20220913061817.22564-7-zong.li@sifive.com Signed-off-by: Palmer Dabbelt

soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes

2022-10-13T18:06:54Z

Use the pr_fmt() macro to prefix all the output with "CCACHE:" to avoid having to write it out each time, or make a large diff when the next change comes along. Signed-off-by: Ben Dooks Signed-off-by: Zong Li Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20220913061817.22564-6-zong.li@sifive.com Signed-off-by: Palmer Dabbelt

soc: sifive: ccache: reduce printing on init

2022-10-13T18:06:53Z

The driver prints out 6 lines on startup, which can easily be redcued to two lines without losing any information. Note, to make the types work better, uint64_t has been replaced with ULL to make the unsigned long long match the format in the print statement. Signed-off-by: Ben Dooks Signed-off-by: Zong Li Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20220913061817.22564-5-zong.li@sifive.com Signed-off-by: Palmer Dabbelt

soc: sifive: ccache: determine the cache level from dts

2022-10-13T18:06:52Z

Composable cache could be L2 or L3 cache, use 'cache-level' property of device node to determine the level. Signed-off-by: Zong Li Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20220913061817.22564-4-zong.li@sifive.com Signed-off-by: Palmer Dabbelt

soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.

2022-10-13T18:06:51Z

Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu Signed-off-by: Zong Li Co-developed-by: Zong Li Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com Signed-off-by: Palmer Dabbelt

RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive FU740

2021-01-08T01:28:27Z

SiFive FU740 has 4 ECC interrupt sources as compared to 3 in FU540. Update the L2 cache controller driver to support this additional interrupt in case of FU740-C000 chip. Signed-off-by: Yash Shah Signed-off-by: Palmer Dabbelt

soc: sifive: l2 cache: Mark l2_get_priv_group as static

2020-05-28T22:57:49Z

The kbuild test robot is firing a warning over a missing prototype. The function can just be static. Reported-by: kbuild test robot Signed-off-by: Palmer Dabbelt

soc: sifive: l2 cache: Eliminate an unsigned zero compare warning

2020-05-28T22:57:48Z

GCC warns about this comparison, which is unnecessary. Signed-off-by: Palmer Dabbelt

riscv: Add support to determine no. of L2 cache way enabled

2020-05-20T22:05:10Z

In order to determine the number of L2 cache ways enabled at runtime, implement a private attribute ("number_of_ways_enabled"). Reading this attribute returns the number of enabled L2 cache ways at runtime. Using riscv_set_cacheinfo_ops() hook a custom function, that returns this private attribute, to the generic ops structure which is used by cache_get_priv_group() in cacheinfo framework. Signed-off-by: Yash Shah Reviewed-by: Anup Patel Signed-off-by: Palmer Dabbelt

riscv: move sifive_l2_cache.h to include/soc

2020-01-12T18:12:44Z

The commit 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc") moves the sifive L2 cache driver to driver/soc. It did not move the header file along with the driver. Therefore this patch moves the header file to driver/soc Signed-off-by: Yash Shah Reviewed-by: Anup Patel [paul.walmsley@sifive.com: updated to fix the include guard] Fixes: 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc") Signed-off-by: Paul Walmsley