<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/drivers/soc/tegra/Kconfig, branch linus/master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/soc/tegra/Kconfig?h=linus%2Fmaster</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/drivers/soc/tegra/Kconfig?h=linus%2Fmaster'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2022-05-04T09:09:49Z</updated>
<entry>
<title>soc/tegra: pmc: Select REGMAP</title>
<updated>2022-05-04T09:09:49Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2022-05-04T09:08:14Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=9767d1be1529c40469d1bbdc457953f88fa1dca7'/>
<id>urn:sha1:9767d1be1529c40469d1bbdc457953f88fa1dca7</id>
<content type='text'>
Commit 9d5e7c3e36eb ("soc/tegra: pmc: Provide USB sleepwalk register
map") introduced a dependency on the regmap infrastructure, so select
the corresponding Kconfig entry. This avoids failures in random builds
that may otherwise end up having SOC_TEGRA_PMC enabled but not REGMAP.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: Make regulator couplers depend on CONFIG_REGULATOR</title>
<updated>2021-08-02T12:30:46Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2021-07-21T23:26:16Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=a4282f66d90e93aacfe1b19509fd5851bf95be68'/>
<id>urn:sha1:a4282f66d90e93aacfe1b19509fd5851bf95be68</id>
<content type='text'>
The regulator coupler drivers now use regulator-driver API function that
isn't available during compile-testing. Make regulator coupler drivers
dependent on CONFIG_REGULATOR in Kconfig.

Fixes: 03978d42ed0d ("soc/tegra: regulators: Bump voltages on system reboot")
Reported-by: kernel test robot &lt;lkp@intel.com&gt;
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Acked-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>soc/tegra: pmc: Add core power domain</title>
<updated>2021-06-02T08:58:42Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2021-06-01T02:31:17Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=f880ee9e96887786dc21e9433ede1719bc3b2624'/>
<id>urn:sha1:f880ee9e96887786dc21e9433ede1719bc3b2624</id>
<content type='text'>
NVIDIA Tegra SoCs have multiple power domains, each domain corresponds
to an external SoC power rail. Core power domain covers vast majority of
hardware blocks within a Tegra SoC. The voltage of a power domain should
be set to a level which satisfies all devices within the power domain.
Add support for the core power domain which controls voltage state of the
domain. This allows us to support system-wide DVFS on Tegra20-210 SoCs.
The PMC powergate domains now are sub-domains of the core domain, this
requires device-tree updating, older DTBs are unaffected and will continue
to work as before.

Tested-by: Peter Geis &lt;pgwipeout@gmail.com&gt; # Ouya T30
Tested-by: Paul Fertser &lt;fercerpav@gmail.com&gt; # PAZ00 T20
Tested-by: Nicolas Chauvet &lt;kwizart@gmail.com&gt; # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar &lt;mattmerhar@protonmail.com&gt; # Ouya T30
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Reviewed-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
[treding@nvidia.com: squash lockdep class removal patch]
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>arm64: tegra: Initial Tegra234 VDK support</title>
<updated>2020-09-18T13:58:07Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2020-09-17T10:07:52Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=639448912ba17a9af9e759efbab37d36c6e29dea'/>
<id>urn:sha1:639448912ba17a9af9e759efbab37d36c6e29dea</id>
<content type='text'>
The NVIDIA Tegra234 VDK is a simulation platform for the Orin SoC. It
supports a subset of the peripherals that will be available in the final
chip and serves as a bootstrapping platform.

Reviewed-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: pmc: Select GENERIC_PINCONF</title>
<updated>2020-05-07T19:23:00Z</updated>
<author>
<name>Corentin Labbe</name>
<email>clabbe@baylibre.com</email>
</author>
<published>2020-03-18T15:25:08Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=5098e2b95e8e6f56266c2d5c180c75917090082a'/>
<id>urn:sha1:5098e2b95e8e6f56266c2d5c180c75917090082a</id>
<content type='text'>
I have hit the following build error:
armv7a-hardfloat-linux-gnueabi-ld: drivers/soc/tegra/pmc.o: in function `pinconf_generic_dt_node_to_map_pin':
pmc.c:(.text+0x500): undefined reference to `pinconf_generic_dt_node_to_map'
armv7a-hardfloat-linux-gnueabi-ld: drivers/soc/tegra/pmc.o:(.rodata+0x1f88): undefined reference to `pinconf_generic_dt_free_map'

So SOC_TEGRA_PMC should select GENERIC_PINCONF.

Fixes: 4a37f11c8f57 ("soc/tegra: pmc: Implement pad configuration via pinctrl")
Cc: stable &lt;stable@vger.kernel.org&gt;
Signed-off-by: Corentin Labbe &lt;clabbe@baylibre.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: fuse: Add APB DMA dependency for Tegra20</title>
<updated>2020-01-10T14:30:11Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2019-12-29T15:01:21Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=19d41e5e9c6863ada69e4f6d006634e60987c7ac'/>
<id>urn:sha1:19d41e5e9c6863ada69e4f6d006634e60987c7ac</id>
<content type='text'>
Tegra20 FUSE driver depends on DMA channel presence, otherwise it fails to
probe.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: regulators: Add regulators coupler for Tegra30</title>
<updated>2019-10-29T13:02:59Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2019-07-25T15:18:32Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=783807436f363e5b1ad4d43ba7debbedfcadbb99'/>
<id>urn:sha1:783807436f363e5b1ad4d43ba7debbedfcadbb99</id>
<content type='text'>
Add regulators coupler for Tegra30 SoCs that performs voltage balancing
of a coupled regulators and thus provides voltage scaling functionality.

There are 2 coupled regulators on all Tegra30 SoCs: CORE and CPU. The
coupled regulator voltages shall be in a range of 300mV from each other
and CORE voltage shall be higher than the CPU by N mV, where N depends
on the CPU voltage.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Acked-By: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: regulators: Add regulators coupler for Tegra20</title>
<updated>2019-10-29T13:02:59Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2019-07-25T15:18:31Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=496747e7d907b01bd2507d61bdd6874b987c9629'/>
<id>urn:sha1:496747e7d907b01bd2507d61bdd6874b987c9629</id>
<content type='text'>
Add regulators coupler for Tegra20 SoCs that performs voltage balancing
of a coupled regulators and thus provides voltage scaling functionality.

There are 3 coupled regulators on all Tegra20 SoCs: CORE, RTC and CPU.
The CORE and RTC voltages shall be in range of 170mV from each other and
they both shall be higher than the CPU voltage by at least 120mV. This
sounds like it could be handle by a generic voltage balancer, but the CORE
voltage scaling isn't implemented in any of the upstream drivers yet.
It will take quite some time and effort to hook up voltage scaling for
all of the drivers, hence we will use a custom coupler that will manage
the CPU voltage scaling for the starter.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Acked-By: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'tegra-for-5.3-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers</title>
<updated>2019-06-25T12:42:42Z</updated>
<author>
<name>Olof Johansson</name>
<email>olof@lixom.net</email>
</author>
<published>2019-06-25T12:42:42Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=761d3d22fb74232d2a5a2899358ff1bab94d6fa0'/>
<id>urn:sha1:761d3d22fb74232d2a5a2899358ff1bab94d6fa0</id>
<content type='text'>
soc: tegra: Changes for v5.3-rc1

This contains a set of minor fixes and cleanups for core Tegra drivers.

* tag 'tegra-for-5.3-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  soc/tegra: Select pinctrl for Tegra194
  soc/tegra: fuse: Do not log error message on deferred probe
  soc/tegra: pmc: Add comments clarifying wake events
  soc/tegra: pmc: Avoid crash for non-wake IRQs
  soc/tegra: pmc: Fail to allocate more than one wake IRQ

Signed-off-by: Olof Johansson &lt;olof@lixom.net&gt;
</content>
</entry>
<entry>
<title>soc/tegra: Select pinctrl for Tegra194</title>
<updated>2019-06-13T08:44:08Z</updated>
<author>
<name>Krishna Yarlagadda</name>
<email>kyarlagadda@nvidia.com</email>
</author>
<published>2019-05-16T11:53:14Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=7ac13f6dcbd59b8f99395588cd7ef31f7e3bd3c6'/>
<id>urn:sha1:7ac13f6dcbd59b8f99395588cd7ef31f7e3bd3c6</id>
<content type='text'>
Select PINCTRL_TEGRA194 by default for Tegra194 SoC needed for
dynamically controlling PCIe pins.

Signed-off-by: Krishna Yarlagadda &lt;kyarlagadda@nvidia.com&gt;
Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
