<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/drivers/soc/tegra/fuse, branch master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/soc/tegra/fuse?h=master</id>
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<updated>2022-09-23T16:04:29Z</updated>
<entry>
<title>Merge tag 'tegra-for-6.1-cbb' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers</title>
<updated>2022-09-23T16:04:29Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2022-09-23T16:04:29Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=3919d905351f279593dd7ec35a23a417963f44a3'/>
<id>urn:sha1:3919d905351f279593dd7ec35a23a417963f44a3</id>
<content type='text'>
soc/tegra: cbb: Changes for v6.1-rc1

This introduces the CBB driver that is used to provide (a lot of)
information about SErrors when things go wrong, instead of the kernel
just crashing or hanging.

* tag 'tegra-for-6.1-cbb' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  soc/tegra: cbb: Add support for Tegra241 (Grace)
  soc/tegra: cbb: Add driver for Tegra234 CBB 2.0
  soc/tegra: cbb: Add CBB 1.0 driver for Tegra194
  soc/tegra: Set ERD bit to mask inband errors

Link: https://lore.kernel.org/r/20220916101957.1635854-2-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>soc/tegra: fuse: Add missing of_node_put()</title>
<updated>2022-09-15T10:38:43Z</updated>
<author>
<name>Liang He</name>
<email>windhl@126.com</email>
</author>
<published>2022-06-15T12:32:32Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=0a3c2dbec425b82d9af7aeb5dc9b18da398992a7'/>
<id>urn:sha1:0a3c2dbec425b82d9af7aeb5dc9b18da398992a7</id>
<content type='text'>
In tegra_init_apbmisc(), of_find_matching_node() will return a node
pointer with refcount incremented. We should use of_node_put() in each
failure path or when it is not used anymore.

Signed-off-by: Liang He &lt;windhl@126.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: fuse: Add missing of_node_put() in tegra_init_fuse()</title>
<updated>2022-09-15T10:38:43Z</updated>
<author>
<name>Liang He</name>
<email>windhl@126.com</email>
</author>
<published>2022-06-16T01:46:36Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=e941712cccab8a96f03b5d3274159c1ed338efee'/>
<id>urn:sha1:e941712cccab8a96f03b5d3274159c1ed338efee</id>
<content type='text'>
In this function, of_find_matching_node() will return a node pointer
with refcount incremented. We should use of_node_put() when the "np"
pointer is not used anymore.

Signed-off-by: Liang He &lt;windhl@126.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: Set ERD bit to mask inband errors</title>
<updated>2022-09-15T10:30:11Z</updated>
<author>
<name>Sumit Gupta</name>
<email>sumitg@nvidia.com</email>
</author>
<published>2022-05-11T20:16:43Z</published>
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<id>urn:sha1:96765cc47546fe6724825600afa8ba170671da61</id>
<content type='text'>
Add a function to set the ERD (Error Response Disable) bit in the
MISCREG_CCROC_ERR_CONFIG register from the Control Backbone (CBB) error
handler driver.

ERD bit allows masking of SError due to inband errors which are caused
by illegal register accesses through CBB. When the bit is set, interrupt
is used for reporting errors and magic code '0xdead2003' is returned.
This change is only required for Tegra194 SoC as the config is moved to
CBB register space for future SoC's. Also, remove unmapping the
apbmisc_base as it's required to get the base address for accessing the
misc register.

Signed-off-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: fuse: Add nvmem cell lookup entries for Tegra194</title>
<updated>2022-04-06T12:55:50Z</updated>
<author>
<name>Sagar Kamble</name>
<email>skamble@nvidia.com</email>
</author>
<published>2022-03-24T12:08:48Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=942501661fa65f13bf9b5582e8248e92770b2d93'/>
<id>urn:sha1:942501661fa65f13bf9b5582e8248e92770b2d93</id>
<content type='text'>
Add nvmem cell lookup entries for below FUSE cells:
 - gcplex-config-fuse
 - pdi0
 - pdi1

Also include the device name prefix "gpu-" in the names of the GPU FUSE
cells in nvmem_cell_info.

Signed-off-by: Sagar Kamble &lt;skamble@nvidia.com&gt;
Reviewed-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: fuse: Explicitly cast to/from __iomem</title>
<updated>2022-02-24T16:09:13Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2022-02-24T12:27:28Z</published>
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<id>urn:sha1:b631c9c2ae934ce2a563853e8e6a591f7d34b48b</id>
<content type='text'>
sparse is picky about casts between different address spaces. A cast to
plain void * needs to be accompanied by a __force modifier and casting
back to void __iomem * needs to be explicit to avoid warnings.

Reported-by: kernel test robot &lt;lkp@intel.com&gt;
Fixes: 88724b78a84c ("soc/tegra: fuse: Use resource-managed helpers")
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Reviewed-by: Dmitry Osipenko &lt;dmitry.osipenko@collabora.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: fuse: Update nvmem cell list</title>
<updated>2022-02-24T16:09:13Z</updated>
<author>
<name>kartik</name>
<email>kkartik@nvidia.com</email>
</author>
<published>2021-12-06T11:52:45Z</published>
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<id>urn:sha1:6f259bf1619bbff6118c1e556044c0cb4020bbb6</id>
<content type='text'>
Update tegra_fuse_cells with below entries:

 - gcplex-config-fuse:
     Configuration bits for GPU, used to enable/disable write protected
     region used for storing GPU firmware.
 - pdi0:
     Unique per chip public identifier.
 - pdi1:
     Unique per chip public identifier.

Signed-off-by: Prathamesh Shete &lt;pshete@nvidia.com&gt;
Signed-off-by: Kartik &lt;kkartik@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'drivers-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc</title>
<updated>2022-01-10T16:13:52Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2022-01-10T16:13:52Z</published>
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<id>urn:sha1:e85195d5bf8979f6db3f12cf8f1294887bf6b037</id>
<content type='text'>
Pull ARM SoC driver updates from Arnd Bergmann:
 "There are cleanups and minor bugfixes across several SoC specific
  drivers, for Qualcomm, Samsung, NXP i.MX, AT91, Tegra, Keystone,
  Renesas, ZynqMP

  Noteworthy new features are:

   - The op-tee firmware driver gains support for asynchronous
     notifications from secure-world firmware.

   - Qualcomm platforms gain support for new SoC types in various
     drivers: power domain, cache controller, RPM sleep, soc-info

   - Samsung SoC drivers gain support for new SoCs in ChipID and PMU, as
     well as a new USIv2 driver that handles various types of serial
     communiction (uart, i2c, spi)

   - Renesas adds support for R-Car S4-8 (R8A779F0) in multiple drivers,
     as well as memory controller support for RZ/G2L (R9A07G044).

   - Apple M1 gains support for the PMGR power management driver"

* tag 'drivers-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (94 commits)
  soc: qcom: rpmh-rsc: Fix typo in a comment
  soc: qcom: socinfo: Add SM6350 and SM7225
  dt-bindings: arm: msm: Don't mark LLCC interrupt as required
  dt-bindings: firmware: scm: Add SM6350 compatible
  dt-bindings: arm: msm: Add LLCC for SM6350
  soc: qcom: rpmhpd: Sort power-domain definitions and lists
  soc: qcom: rpmhpd: Remove mx/cx relationship on sc7280
  soc: qcom: rpmhpd: Rename rpmhpd struct names
  soc: qcom: rpmhpd: sm8450: Add the missing .peer for sm8450_cx_ao
  soc: qcom: socinfo: add SM8450 ID
  soc: qcom: rpmhpd: Add SM8450 power domains
  dt-bindings: power: rpmpd: Add SM8450 to rpmpd binding
  soc: qcom: smem: Update max processor count
  dt-bindings: arm: qcom: Document SM8450 SoC and boards
  dt-bindings: firmware: scm: Add SM8450 compatible
  dt-bindings: arm: cpus: Add kryo780 compatible
  soc: qcom: rpmpd: Add support for sm6125
  dt-bindings: qcom-rpmpd: Add sm6125 power domains
  soc: qcom: aoss: constify static struct thermal_cooling_device_ops
  PM: AVS: qcom-cpr: Use div64_ul instead of do_div
  ...
</content>
</entry>
<entry>
<title>soc/tegra: fuse: Use resource-managed helpers</title>
<updated>2021-12-16T13:03:38Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2021-11-30T23:23:36Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=88724b78a84c85350c21ac8d4432f2cf5a77a10a'/>
<id>urn:sha1:88724b78a84c85350c21ac8d4432f2cf5a77a10a</id>
<content type='text'>
Use resource-managed helpers to make code cleaner and more correct,
properly releasing all resources in case of driver probe error.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: fuse: Reset hardware</title>
<updated>2021-12-16T13:03:38Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2021-11-30T23:23:35Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=aeecc50ace0480e6df565093e578b129902918db'/>
<id>urn:sha1:aeecc50ace0480e6df565093e578b129902918db</id>
<content type='text'>
The FUSE controller is enabled at a boot time. Reset it in order to put
hardware and clock into clean and disabled state.

Reviewed-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
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