<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/drivers/soc, branch master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/soc?h=master</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/drivers/soc?h=master'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2022-10-29T08:26:32Z</updated>
<entry>
<title>soc: imx: imx93-pd: Fix the error handling path of imx93_pd_probe()</title>
<updated>2022-10-29T08:26:32Z</updated>
<author>
<name>Christophe JAILLET</name>
<email>christophe.jaillet@wanadoo.fr</email>
</author>
<published>2022-10-22T06:08:55Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=0ba7b623f15d52fa056eca26573d8cf1b9c29fd1'/>
<id>urn:sha1:0ba7b623f15d52fa056eca26573d8cf1b9c29fd1</id>
<content type='text'>
In imx93_pd_probe(); if an error occurs, some resources need to be released
as done in the remove function.

Fixes: 0a0f7cc25d4a ("soc: imx: add i.MX93 SRC power domain driver")
Signed-off-by: Christophe JAILLET &lt;christophe.jaillet@wanadoo.fr&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge patch series "Use composable cache instead of L2 cache"</title>
<updated>2022-10-13T18:07:13Z</updated>
<author>
<name>Palmer Dabbelt</name>
<email>palmer@rivosinc.com</email>
</author>
<published>2022-10-13T18:06:57Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=1a5a2cbd21e58a824688ae2120a3e47b3cd0f876'/>
<id>urn:sha1:1a5a2cbd21e58a824688ae2120a3e47b3cd0f876</id>
<content type='text'>
Zong Li &lt;zong.li@sifive.com&gt; says:

Since composable cache may be L3 cache if private L2 cache exists, we
should use its original name "composable cache" to prevent confusion.

This patchset contains the modification which is related to ccache, such
as DT binding and EDAC driver.

* b4-shazam-merge:
  riscv: Add cache information in AUX vector
  soc: sifive: ccache: define the macro for the register shifts
  soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes
  soc: sifive: ccache: reduce printing on init
  soc: sifive: ccache: determine the cache level from dts
  soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.
  dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache

Link: https://lore.kernel.org/r/20220913061817.22564-1-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>soc: sifive: ccache: define the macro for the register shifts</title>
<updated>2022-10-13T18:06:55Z</updated>
<author>
<name>Zong Li</name>
<email>zong.li@sifive.com</email>
</author>
<published>2022-09-13T06:18:16Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=afc7a5834f0de13aee46df62f09e479c1bbf7b9d'/>
<id>urn:sha1:afc7a5834f0de13aee46df62f09e479c1bbf7b9d</id>
<content type='text'>
Define the macro for the register shifts, it could make the code be
more readable

Signed-off-by: Zong Li &lt;zong.li@sifive.com&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Link: https://lore.kernel.org/r/20220913061817.22564-7-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes</title>
<updated>2022-10-13T18:06:54Z</updated>
<author>
<name>Ben Dooks</name>
<email>ben.dooks@sifive.com</email>
</author>
<published>2022-09-13T06:18:15Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=696ab9bda22a770d079dc3a23bac9aaa553d98f4'/>
<id>urn:sha1:696ab9bda22a770d079dc3a23bac9aaa553d98f4</id>
<content type='text'>
Use the pr_fmt() macro to prefix all the output with "CCACHE:"
to avoid having to write it out each time, or make a large diff
when the next change comes along.

Signed-off-by: Ben Dooks &lt;ben.dooks@sifive.com&gt;
Signed-off-by: Zong Li &lt;zong.li@sifive.com&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Link: https://lore.kernel.org/r/20220913061817.22564-6-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>soc: sifive: ccache: reduce printing on init</title>
<updated>2022-10-13T18:06:53Z</updated>
<author>
<name>Ben Dooks</name>
<email>ben.dooks@sifive.com</email>
</author>
<published>2022-09-13T06:18:14Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=3fb787e5bad50687a65ded7f3bb805cab70dff59'/>
<id>urn:sha1:3fb787e5bad50687a65ded7f3bb805cab70dff59</id>
<content type='text'>
The driver prints out 6 lines on startup, which can easily be redcued
to two lines without losing any information.

Note, to make the types work better, uint64_t has been replaced with
ULL to make the unsigned long long match the format in the print
statement.

Signed-off-by: Ben Dooks &lt;ben.dooks@sifive.com&gt;
Signed-off-by: Zong Li &lt;zong.li@sifive.com&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Link: https://lore.kernel.org/r/20220913061817.22564-5-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>soc: sifive: ccache: determine the cache level from dts</title>
<updated>2022-10-13T18:06:52Z</updated>
<author>
<name>Zong Li</name>
<email>zong.li@sifive.com</email>
</author>
<published>2022-09-13T06:18:13Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=95f196f3212bbc258611c22865aef12b98304e1d'/>
<id>urn:sha1:95f196f3212bbc258611c22865aef12b98304e1d</id>
<content type='text'>
Composable cache could be L2 or L3 cache, use 'cache-level' property of
device node to determine the level.

Signed-off-by: Zong Li &lt;zong.li@sifive.com&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Link: https://lore.kernel.org/r/20220913061817.22564-4-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.</title>
<updated>2022-10-13T18:06:51Z</updated>
<author>
<name>Greentime Hu</name>
<email>greentime.hu@sifive.com</email>
</author>
<published>2022-09-13T06:18:12Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=ca120a79cf5a3323172c82e77efd70ae10d120ef'/>
<id>urn:sha1:ca120a79cf5a3323172c82e77efd70ae10d120ef</id>
<content type='text'>
Since composable cache may be L3 cache if there is a L2 cache, we should
use its original name composable cache to prevent confusion.

There are some new lines were generated due to adding the compatible
"sifive,ccache0" into ID table and indent requirement.

The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to
apply the change as well.

Signed-off-by: Greentime Hu &lt;greentime.hu@sifive.com&gt;
Signed-off-by: Zong Li &lt;zong.li@sifive.com&gt;
Co-developed-by: Zong Li &lt;zong.li@sifive.com&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'char-misc-6.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc</title>
<updated>2022-10-08T15:56:37Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2022-10-08T15:56:37Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=a09476668e3016ea4a7b0a7ebd02f44e0546c12c'/>
<id>urn:sha1:a09476668e3016ea4a7b0a7ebd02f44e0546c12c</id>
<content type='text'>
Pull char/misc and other driver updates from Greg KH:
 "Here is the large set of char/misc and other small driver subsystem
  changes for 6.1-rc1. Loads of different things in here:

   - IIO driver updates, additions, and changes. Probably the largest
     part of the diffstat

   - habanalabs driver update with support for new hardware and
     features, the second largest part of the diff.

   - fpga subsystem driver updates and additions

   - mhi subsystem updates

   - Coresight driver updates

   - gnss subsystem updates

   - extcon driver updates

   - icc subsystem updates

   - fsi subsystem updates

   - nvmem subsystem and driver updates

   - misc driver updates

   - speakup driver additions for new features

   - lots of tiny driver updates and cleanups

  All of these have been in the linux-next tree for a while with no
  reported issues"

* tag 'char-misc-6.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (411 commits)
  w1: Split memcpy() of struct cn_msg flexible array
  spmi: pmic-arb: increase SPMI transaction timeout delay
  spmi: pmic-arb: block access for invalid PMIC arbiter v5 SPMI writes
  spmi: pmic-arb: correct duplicate APID to PPID mapping logic
  spmi: pmic-arb: add support to dispatch interrupt based on IRQ status
  spmi: pmic-arb: check apid against limits before calling irq handler
  spmi: pmic-arb: do not ack and clear peripheral interrupts in cleanup_irq
  spmi: pmic-arb: handle spurious interrupt
  spmi: pmic-arb: add a print in cleanup_irq
  drivers: spmi: Directly use ida_alloc()/free()
  MAINTAINERS: add TI ECAP driver info
  counter: ti-ecap-capture: capture driver support for ECAP
  Documentation: ABI: sysfs-bus-counter: add frequency &amp; num_overflows items
  dt-bindings: counter: add ti,am62-ecap-capture.yaml
  counter: Introduce the COUNTER_COMP_ARRAY component type
  counter: Consolidate Counter extension sysfs attribute creation
  counter: Introduce the Count capture component
  counter: 104-quad-8: Add Signal polarity component
  counter: Introduce the Signal polarity component
  counter: interrupt-cnt: Implement watch_validate callback
  ...
</content>
</entry>
<entry>
<title>Merge tag 'arm-soc-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc</title>
<updated>2022-10-06T18:22:25Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2022-10-06T18:22:25Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=41fc64a0550b86f4428e8d3fa23ab97678a65ae8'/>
<id>urn:sha1:41fc64a0550b86f4428e8d3fa23ab97678a65ae8</id>
<content type='text'>
Pull ARM SoC updates from Arnd Bergmann:
 "The main changes this time are for the organization of the Kconfig
  files, introducing per-vendor top-level options on arm64 to match
  those on arm32, and making the platform selection on arm32 more
  uniform, in particular for the remaining StrongARM platforms that
  still have a couple of special cases compared to the more recent ones.

  I also did a cleanup of the old Footbridge platform, which was the
  last holdout for the phys_to_dma()/dma_to_phys() interface that is now
  completely gone from arm32, completing work started by Christoph
  Hellwig"

* tag 'arm-soc-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (21 commits)
  ARM: aspeed: Kconfig: Fix indentation
  ARM: Drop CMDLINE_* dependency on ATAGS
  ARM: Drop CMDLINE_FORCE dependency on !ARCH_MULTIPLATFORM
  ARM: s3c: remove orphan declarations from arch/arm/mach-s3c/devs.h
  pxa: Drop if with an always false condition
  ARM: orion: fix include path
  ARM: shmobile: Drop selecting SOC_BUS
  arm64: renesas: Drop selecting SOC_BUS
  ARM: disallow PCI with MMU=n again
  ARM: footbridge: remove custom DMA address handling
  MAINTAINERS: Add BCM4908 maintainer to BCMBCA entry
  ARM: footbridge: move isa-dma support into footbridge
  ARM: footbridge: remove leftover from personal-server
  ARM: footbridge: remove addin mode
  arm64: Kconfig.platforms: Group NXP platforms together
  arm64: Kconfig.platforms: Re-organized Broadcom menu
  ARM: make ARCH_MULTIPLATFORM user-visible
  ARM: fix XIP_KERNEL dependencies
  ARM: Kconfig: clean up platform selection
  ARM: simplify machdirs/platdirs handling
  ...
</content>
</entry>
<entry>
<title>Merge tag 'arm-drivers-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc</title>
<updated>2022-10-06T18:04:57Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2022-10-06T18:04:57Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=ff6862c23d2e83d12d1759bf4337d41248fb4dc8'/>
<id>urn:sha1:ff6862c23d2e83d12d1759bf4337d41248fb4dc8</id>
<content type='text'>
Pull ARM driver updates from Arnd Bergmann:
 "The drivers branch for 6.1 is a bit larger than for most releases.

  Most of the changes come from SoC maintainers for the drivers/soc
  subsystem:

   - A new driver for error handling on the NVIDIA Tegra 'control
     backbone' bus.

   - A new driver for Qualcomm LLCC/DDR bandwidth measurement

   - New Rockchip rv1126 and rk3588 power domain drivers

   - DT binding updates for memory controllers, older Rockchip SoCs,
     various Mediatek devices, Qualcomm SCM firmware

   - Minor updates to Hisilicon LPC bus, the Allwinner SRAM driver, the
     Apple rtkit firmware driver, Tegra firmware

   - Minor updates for SoC drivers (Samsung, Mediatek, Renesas, Tegra,
     Qualcomm, Broadcom, NXP, ...)

  There are also some separate subsystem with downstream maintainers
  that merge updates this way:

   - Various updates and new drivers in the memory controller subsystem
     for Mediatek and Broadcom SoCs

   - Small set of changes in preparation to add support for FF-A v1.1
     specification later, in the Arm FF-A firmware subsystem

   - debugfs support in the PSCI firmware subsystem"

* tag 'arm-drivers-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (149 commits)
  ARM: remove check for CONFIG_DEBUG_LL_SER3
  firmware/psci: Add debugfs support to ease debugging
  firmware/psci: Print a warning if PSCI doesn't accept PC mode
  dt-bindings: memory: snps,dw-umctl2-ddrc: Extend schema with IRQs/resets/clocks props
  dt-bindings: memory: snps,dw-umctl2-ddrc: Replace opencoded numbers with macros
  dt-bindings: memory: snps,dw-umctl2-ddrc: Use more descriptive device name
  dt-bindings: memory: synopsys,ddrc-ecc: Detach Zynq DDRC controller support
  soc: sunxi: sram: Add support for the D1 system control
  soc: sunxi: sram: Export the LDO control register
  soc: sunxi: sram: Save a pointer to the OF match data
  soc: sunxi: sram: Return void from the release function
  soc: apple: rtkit: Add apple_rtkit_poll
  soc: imx: add i.MX93 media blk ctrl driver
  soc: imx: add i.MX93 SRC power domain driver
  soc: imx: imx8m-blk-ctrl: Use genpd_xlate_onecell
  soc: imx: imx8mp-blk-ctrl: handle PCIe PHY resets
  soc: imx: imx8m-blk-ctrl: add i.MX8MP VPU blk ctrl
  soc: imx: add i.MX8MP HDMI blk ctrl HDCP/HRV_MWR
  soc: imx: add icc paths for i.MX8MP hsio/hdmi blk ctrl
  soc: imx: add icc paths for i.MX8MP media blk ctrl
  ...
</content>
</entry>
</feed>
