linux-dev/drivers/staging/mt7621-pci, branch master

PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver

2021-10-21T15:59:18Z

Add driver for the PCIe controller of the MT7621 SoC. [bhelgaas: rename from pci-mt7621.c to pcie-mt7621.c; also rename Kconfig symbol from PCI_MT7621 to PCIE_MT7621] Link: https://lore.kernel.org/r/20210922050035.18162-3-sergio.paracuellos@gmail.com Signed-off-by: Sergio Paracuellos Signed-off-by: Lorenzo Pieralisi Signed-off-by: Bjorn Helgaas Acked-by: Greg Kroah-Hartman

staging: mt7621-pci: fix hang when nothing is connected to pcie ports

2021-08-26T10:06:37Z

When nothing is connected to pcie ports, each port is set to reset state. When this occurs, next access result in a hang on boot as follows: mt7621-pci 1e140000.pcie: pcie0 no card, disable it (RST & CLK) mt7621-pci 1e140000.pcie: pcie1 no card, disable it (RST & CLK) mt7621-pci 1e140000.pcie: pcie2 no card, disable it (RST & CLK) [ HANGS HERE ] Fix this just detecting 'nothing is connected state' to avoid next accesses to pcie port related configuration registers. Fixes: b99cc3a2b6b6 ("staging: mt7621-pci: avoid custom 'map_irq' function") Cc: stable Reported-by: DENG Qingfang Signed-off-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20210823170803.2108-1-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman

staging: mt7621-pci: avoid to re-disable clock for those pcies not in use

2021-07-27T13:48:43Z

Clock driver for this SoC is using some gates to properly enabling and disabling the access to peripherals. Those gates that are not in use are properly being automatically disabled by the kernel. Pcie driver is explicitly doing a 'clk_disable_unprepare' call for gates of those pcies that are not used. Since kernel has already disabled them, the following warnings appear: WARNING: CPU: 0 PID: 1 at drivers/clk/clk.c:952 clk_core_disable+0xe4/0x100 pcie2 already disabled Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.14.0 #0 Stack : 81661680 80082d00 807c0000 00000004 00000000 80a20000 80860000 80792380 814503d4 80862e83 00000000 1431b70 81454360 00000000 00000000 80792380 81431a08 ffffefff fffffea 00000000 81431a14 0000007b 80868820 ffffffff 80792380 1431c70 803d7a24 00000009 807f3a74 00000001 815df810 00000018 0000000 80a20000 ... Call Trace: [<80007ed8>] show_stack+0x28/0xf0 [<80381e40>] dump_stack_lvl+0x60/0x80 [<8002cf90>] __warn+0xcc/0x140 [<8002d090>] warn_slowpath_fmt+0x8c/0xac [<803d7a24>] clk_core_disable+0xe4/0x100 [<803da468>] clk_disable+0x38/0x58 [<804cb730>] mt7621_pci_probe+0x980/0xa50 [<8041e624>] platform_probe+0x50/0xbc [<8041bfe4>] really_probe.part.0+0xa8/0x340 [<8041c3dc>] driver_probe_device+0x4c/0x154 [<8041cb88>] __driver_attach+0xb4/0x1b4 [<80419a38>] bus_for_each_dev+0x68/0xa4 [<8041b1e8>] bus_add_driver+0x134/0x214 [<8041d3bc>] driver_register+0x98/0x154 [<80001648>] do_one_initcall+0x50/0x1a8 [<808ea1fc>] kernel_init_freeable+0x270/0x30c [<806dd9dc>] kernel_init+0x20/0x110 [<80002d98>] ret_from_kernel_thread+0x14/0x1c WARNING: CPU: 0 PID: 1 at drivers/clk/clk.c:810 clk_core_unprepare+0xf4/0x194 pcie2 already unprepared Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 5.14.0 #0 Stack : 81661680 80082d00 807c0000 00000004 00000000 00000000 81431bc4 80a20000 80860000 80792380 814503d4 80862e83 00000000 00000001 81431b70 81454360 00000000 00000000 80792380 81431a08 ffffefff 00000000 ffffffea 00000000 81431a14 0000009b 80868820 ffffffff 80792380 00000001 81431c70 803d7764 00000009 807f3a74 00000001 815df810 00000018 8040b36c 00000000 80a20000 ... Call Trace: [<80007ed8>] show_stack+0x28/0xf0 [<80381e40>] dump_stack_lvl+0x60/0x80 [<8002cf90>] __warn+0xcc/0x140 [<8002d090>] warn_slowpath_fmt+0x8c/0xac [<803d7764>] clk_core_unprepare+0xf4/0x194 [<803d97c4>] clk_unprepare+0x30/0x48 [<804cb738>] mt7621_pci_probe+0x988/0xa50 [<8041e624>] platform_probe+0x50/0xbc [<8041bfe4>] really_probe.part.0+0xa8/0x340 [<8041c3dc>] driver_probe_device+0x4c/0x154 [<8041cb88>] __driver_attach+0xb4/0x1b4 [<80419a38>] bus_for_each_dev+0x68/0xa4 [<8041b1e8>] bus_add_driver+0x134/0x214 [<8041d3bc>] driver_register+0x98/0x154 [<80001648>] do_one_initcall+0x50/0x1a8 [<808ea1fc>] kernel_init_freeable+0x270/0x30c [<806dd9dc>] kernel_init+0x20/0x110 [<80002d98>] ret_from_kernel_thread+0x14/0x1c Avoid to explicitly disable already disabled pcie gates fixes the problem. Fixes: cc4e864a5ce4 ("staging: mt7621-pci: make use of kernel clock apis") Reported-by: DENG Qingfang Signed-off-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20210727054058.10612-1-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman

staging: mt7621-pci: remove 'mt7621_pci_parse_request_of_pci_ranges'

2021-06-15T13:24:29Z

After 'PCI_IOBASE' is defined for ralink, ranges are properly parsed using pci generic APIS and there is no need to parse anything manually. So function 'mt7621_pci_parse_request_of_pci_ranges' used for this can be enterely removed. Since we have to configure iocu memory regions and pci io windows resources must be retrieved accordly from 'bridge->windows' but there is no need to store anything as driver private data. Signed-off-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20210614100617.28753-3-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman

staging: mt7621-pci: make use of 'pcie_port_write'

2021-06-09T12:19:22Z

Function 'mt7621_pcie_enable_port' is calculating an offset to write some port related registers. Instead of doing that just make use of already existent 'pcie_write_port' function and use virtualy mapped base address with registers. This increase readability and allow us to remove also two defitions not used else where. Signed-off-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20210607120153.24989-7-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman

staging: mt7621-pci: parse some dt properties from root port child nodes

2021-06-09T12:19:22Z

Properties 'clocks', 'resets' and 'phys' have been moved from parent node to the root port children. Hence we have to adapt the way device tree is parsed in driver code to properly align things and make all the stuff work. Note that we moved from using 'devm_reset_control_get_exclusive() to 'of_reset_control_get_exclusive()' so we need to properly call the 'reset_control_put()' function manually in error and remove paths. Signed-off-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20210607120153.24989-6-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman

staging: mt7621-pci: use {readl|writel}_relaxed instead of readl/writel

2021-06-09T12:19:21Z

The driver does not perform DMA, so it's safe to use the relaxed version for both readl and writel operations. Signed-off-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20210607120153.24989-4-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman

staging: mt7621-pci: remove 'RALINK_PCI_BAR0SETUP_ADDR' definition

2021-06-09T12:19:21Z

Instead of define RALINK_PCI_BAR0SETUP_ADDR just use standard pci defnition for this which is 'PCI_BASE_ADDRESS_0'. Signed-off-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20210607120153.24989-3-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman

staging: mt7621-pci: make cleaner 'mt7621_pcie_enable_ports'

2021-06-09T12:19:21Z

Function 'mt7621_pcie_enable_ports' call 'mt7621_pcie_enable_port' for each available pcie port. Instead of having two for loops there just move needed initialization. There is one setting that can be removed which is the set for 'PCI_COMMAND_MASTER' bit. Pci drivers are in charge of set that bit if is really needed and should be not a mission of the controller to do that. Signed-off-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20210607120153.24989-2-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman

staging: mt7621-pci: remove two blank lines

2021-05-10T09:19:40Z

There are useless two blank lines in code that can be removed. Hence, remove them. Signed-off-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20210505121736.6459-9-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman