linux-dev/include/asm-ia64/pal.h, branch master

[IA64] Move include/asm-ia64 to arch/ia64/include/asm

2008-08-01T17:21:21Z

After moving the the include files there were a few clean-ups: 1) Some files used #include , changed to 2) Some comments alerted maintainers to look at various header files to make matching updates if certain code were to be changed. Updated these comments to use the new include paths. 3) Some header files mentioned their own names in initial comments. Just deleted these self references. Signed-off-by: Tony Luck

[IA64] Itanium Spec updates

2008-04-09T20:05:54Z

Updates based on the "Intel® Itanium® Architecture Software Developer's Manual Specification Update October 2007". http://download.intel.com/design/itanium/specupdt/24869911.pdf Signed-off-by: Russ Anderson Signed-off-by: Tony Luck

[IA64] Update printing of feature set bits

2007-11-09T21:05:30Z

Newer Itanium versions have added additional processor feature set bits. This patch prints all the implemented feature set bits. Some bit descriptions have not been made public. For those bits, a generic "Feature set X bit Y" message is printed. Bits that are not implemented will no longer be printed. Signed-off-by: Russ Anderson Signed-off-by: Tony Luck

Pull error-inject into release branch

2007-04-30T20:55:43Z

[IA64] Proper handling of TLB errors from duplicate itr.d dropins

2007-03-08T17:41:46Z

Jack Steiner noticed that duplicate TLB DTC entries do not cause a linux panic. See discussion: http://www.gelato.unsw.edu.au/archives/linux-ia64/0307/6108.html The current TLB recovery code is recovering from the duplicate itr.d dropins, masking the underlying problem. This change modifies the MCA recovery code to look for the TLB check signature of the duplicate TLB entry and panic in that case. Signed-off-by: Russ Anderson (rja@sgi.com) Signed-off-by: Tony Luck

Fix typos concerning hierarchy

2007-02-17T18:23:03Z

heirarchical, hierachical -> hierarchical heirarchy, hierachy -> hierarchy Signed-off-by: Uwe Kleine-König Signed-off-by: Adrian Bunk

[IA64] Itanium MC Error Injection Tool: pal_mc_error_inject() interface

2007-01-29T23:29:56Z

This patch implements pal_mc_error_inject() interface in kernel. Both physical mode and virtual mode are supported. Signed-off-by: Fenghua Yu Signed-off-by: Tony Luck

[PATCH] Add support for type argument in PAL_GET_PSTATE

2006-12-07T19:21:55Z

PAL_GET_PSTATE accepts a type argument to return different kinds of frequency information. Refer: Intel Itanium�Architecture Software Developer's Manual - Volume 2: System Architecture, Revision 2.2 (http://developer.intel.com/design/itanium/manuals/245318.htm) Add the support for type argument and use Instantaneous frequency in the acpi driver. Also fix a bug, where in return value of PAL_GET_PSTATE was getting compared with 'control' bits instead of 'status' bits. Signed-off-by: Venkatesh Pallipadi Signed-off-by: Tony Luck

[IA64] More Itanium PAL spec updates

2006-12-07T19:10:16Z

Additional updates to conform with Rev 2.2 of Volume 2 of "Intel Itanium Architecture Software Developer's Manual" (January 2006). Add pal_bus_features_s bits 52 & 53 (page 2:347) Add pal_vm_info_2_s field max_purges (page 2:2:451) Add PAL_GET_HW_POLICY call (page 2:381) Add PAL_SET_HW_POLICY call (page 2:439) Sample output before: --------------------------------------------------------------------- cobra:~ # cat /proc/pal/cpu0/vm_info Physical Address Space : 50 bits Virtual Address Space : 61 bits Protection Key Registers(PKR) : 16 Implemented bits in PKR.key : 24 Hash Tag ID : 0x2 Size of RR.rid : 24 Supported memory attributes : WB, UC, UCE, WC, NaTPage --------------------------------------------------------------------- Sample output after: --------------------------------------------------------------------- cobra:~ # cat /proc/pal/cpu0/vm_info Physical Address Space : 50 bits Virtual Address Space : 61 bits Protection Key Registers(PKR) : 16 Implemented bits in PKR.key : 24 Hash Tag ID : 0x2 Max Purges : 1 Size of RR.rid : 24 Supported memory attributes : WB, UC, UCE, WC, NaTPage --------------------------------------------------------------------- Signed-off-by: Russ Anderson (rja@sgi.com) Signed-off-by: Tony Luck

[IA64] Add se bit to Processor State Parameter structure

2006-12-07T19:02:53Z

Rev 2.2 of Volume 2 of "Intel Itanium Architecture Software Developer's Manual" (January 2006) adds a se bit to the Processor State Parameter fields (pages 2:299). This patch gets the structs back in sync with the spec. Signed-off-by: Russ Anderson (rja@sgi.com) Signed-off-by: Tony Luck