linux-dev/include/dt-bindings/clock, branch master

Merge tag 'v6.1-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6

2022-10-10T20:04:25Z

Pull crypto updates from Herbert Xu: "API: - Feed untrusted RNGs into /dev/random - Allow HWRNG sleeping to be more interruptible - Create lib/utils module - Setting private keys no longer required for akcipher - Remove tcrypt mode=1000 - Reorganised Kconfig entries Algorithms: - Load x86/sha512 based on CPU features - Add AES-NI/AVX/x86_64/GFNI assembler implementation of aria cipher Drivers: - Add HACE crypto driver aspeed" * tag 'v6.1-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (124 commits) crypto: aspeed - Remove redundant dev_err call crypto: scatterwalk - Remove unused inline function scatterwalk_aligned() crypto: aead - Remove unused inline functions from aead crypto: bcm - Simplify obtain the name for cipher crypto: marvell/octeontx - use sysfs_emit() to instead of scnprintf() hwrng: core - start hwrng kthread also for untrusted sources crypto: zip - remove the unneeded result variable crypto: qat - add limit to linked list parsing crypto: octeontx2 - Remove the unneeded result variable crypto: ccp - Remove the unneeded result variable crypto: aspeed - Fix check for platform_get_irq() errors crypto: virtio - fix memory-leak crypto: cavium - prevent integer overflow loading firmware crypto: marvell/octeontx - prevent integer overflows crypto: aspeed - fix build error when only CRYPTO_DEV_ASPEED is enabled crypto: hisilicon/qm - fix the qos value initialization crypto: sun4i-ss - use DEFINE_SHOW_ATTRIBUTE to simplify sun4i_ss_debugfs crypto: tcrypt - add async speed test for aria cipher crypto: aria-avx - add AES-NI/AVX/x86_64/GFNI assembler implementation of aria cipher crypto: aria - prepare generic module for optimized implementations ...

Merge branches 'clk-fixed-rate', 'clk-spreadtrum', 'clk-pxa' and 'clk-ti' into clk-next

2022-10-04T17:54:14Z

- More devm helpers for fixed rate registration - Add Spreadtrum UMS512 SoC clk support - Various PXA168 clk driver fixes * clk-fixed-rate: clk: fixed-rate: add devm_clk_hw_register_fixed_rate clk: asm9260: use parent index to link the reference clock * clk-spreadtrum: clk: sprd: Add clocks support for UMS512 * clk-pxa: clk: pxa: add a check for the return value of kzalloc() clk: mmp: pxa168: control shared SDH bits with separate clock dt-bindings: marvell,pxa168: add clock ids for SDH AXI clocks clk: mmp: pxa168: add clocks for SDH2 and SDH3 dt-bindings: marvell,pxa168: add clock id for SDH3 clk: mmp: pxa168: fix GPIO clock enable bits clk: mmp: pxa168: add muxes for more peripherals clk: mmp: pxa168: fix incorrect parent clocks clk: mmp: pxa168: fix const-correctness clk: mmp: pxa168: add new clocks for peripherals dt-bindings: marvell,pxa168: add clock ids for additional dividers clk: mmp: pxa168: fix incorrect dividers clk: mmp: pxa168: add additional register defines * clk-ti: clk: davinci: cfgchip: Use dev_err_probe() helper clk: davinci: pll: fix spelling typo in comment MAINTAINERS: add header file to TI DAVINCI SERIES CLOCK DRIVER

Merge branches 'clk-rockchip', 'clk-renesas', 'clk-microchip', 'clk-allwinner' and 'clk-imx' into clk-next

2022-10-04T17:54:02Z

* clk-rockchip: dt-bindings: clock: rockchip: change SPDX-License-Identifier dt-bindings: clock: convert rockchip,rk3128-cru.txt to YAML clk: rockchip: Add clock controller support for RV1126 SoC dt-bindings: clock: rockchip: Document RV1126 CRU clk: rockchip: Add dt-binding header for RV1126 clk: rockchip: Add MUXTBL variant * clk-renesas: clk: renesas: r8a779g0: Add EtherAVB clocks clk: renesas: r8a779g0: Add PFC/GPIO clocks clk: renesas: r8a779g0: Add I2C clocks clk: renesas: r8a779g0: Add watchdog clock dt-bindings: clock: renesas,rzg2l: Document RZ/Five SoC clk: renesas: r8a779f0: Add MSIOF clocks clk: renesas: r9a09g011: Add IIC clock and reset entries clk: renesas: r9a07g044: Add conditional compilation for r9a07g044_cpg_info clk: renesas: r8a779f0: Add TMU and parent SASYNC clocks clk: renesas: r8a779f0: Add CMT clocks clk: renesas: r8a779f0: Add SDH0 clock * clk-microchip: clk: at91: sama5d2: Add Generic Clocks for UART/USART clk: microchip: add PolarFire SoC fabric clock support dt-bindings: clk: add PolarFire SoC fabric clock ids dt-bindings: clk: document PolarFire SoC fabric clocks dt-bindings: clk: rename mpfs-clkcfg binding clk: microchip: mpfs: update module authorship & licencing clk: microchip: mpfs: convert periph_clk to clk_gate clk: microchip: mpfs: convert cfg_clk to clk_divider clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo() clk: microchip: mpfs: simplify control reg access clk: microchip: mpfs: move id & offset out of clock structs clk: microchip: mpfs: add MSS pll's set & round rate MAINTAINERS: add polarfire soc reset controller reset: add polarfire soc reset support clk: microchip: mpfs: add reset controller dt-bindings: clk: microchip: mpfs: add reset controller support clk: microchip: mpfs: make the rtc's ahb clock critical clk: microchip: mpfs: fix clk_cfg array bounds violation * clk-allwinner: clk: sunxi-ng: ccu-sun9i-a80-usb: Use dev_err_probe() helper clk: sunxi-ng: ccu-sun9i-a80-de: Use dev_err_probe() helper clk: sunxi-ng: sun8i-de2: Use dev_err_probe() helper clk: sunxi-ng: d1: Limit PLL rates to stable ranges * clk-imx: clk: imx: scu: fix memleak on platform_device_add() fails clk: imx93: add SAI IPG clk clk: imx93: add MU1/2 clock clk: imx93: switch to use new clk gate API clk: imx: add i.MX93 clk gate clk: imx: clk-composite-93: check white_list clk: imx: clk-composite-93: check slice busy dt-bindings: clock: imx93-clock: add more MU/SAI clocks dt-bindings: clock: imx8mm: don't use multiple blank lines clk: imx8mp: tune the order of enet_qos_root_clk

Merge branches 'clk-samsung', 'clk-mtk', 'clk-rm', 'clk-ast' and 'clk-qcom' into clk-next

2022-10-04T17:53:41Z

- Add resets for MediaTek MT8195 PCIe and USB - Remove DaVinci DM644x and DM646x clk driver support * clk-samsung: clk: samsung: MAINTAINERS: add Krzysztof Kozlowski clk: samsung: exynos850: Implement CMU_MFCMSCL domain clk: samsung: exynos850: Implement CMU_IS domain clk: samsung: exynos850: Implement CMU_AUD domain clk: samsung: exynos850: Style fixes clk: samsung: exynosautov9: add fsys1 clock support clk: samsung: exynosautov9: add fsys0 clock support clk: samsung: exynosautov9: correct register offsets of peric0/c1 clk: samsung: exynosautov9: add missing gate clks for peric0/c1 dt-bindings: clock: exynos850: Add Exynos850 CMU_MFCMSCL dt-bindings: clock: exynos850: Add Exynos850 CMU_IS dt-bindings: clock: exynos850: Add Exynos850 CMU_AUD dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1 dt-bindings: clock: exynosautov9: add fsys1 clock definitions dt-bindings: clock: exynosautov9: add fys0 clock definitions clk: samsung: exynos7885: Add TREX clocks clk: samsung: exynos7885: Implement CMU_FSYS domain dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1 clk: samsung: exynos-clkout: Use of_device_get_match_data() * clk-mtk: (42 commits) clk: mediatek: add driver for MT8365 SoC clk: mediatek: Export required common code symbols clk: mediatek: Provide mtk_devm_alloc_clk_data dt-bindings: clock: mediatek: add bindings for MT8365 SoC clk: mediatek: mt8192: deduplicate parent clock lists clk: mediatek: Migrate remaining clk_unregister_*() to clk_hw_unregister_*() clk: mediatek: fix unregister function in mtk_clk_register_dividers cleanup clk: mediatek: clk-mt8192: Add clock mux notifier for mfg_pll_sel clk: mediatek: clk-mt8192-mfg: Propagate rate changes to parent clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents clk: mediatek: clk-mt8195-topckgen: Add GPU clock mux notifier clk: mediatek: clk-mt8195-topckgen: Register mfg_ck_fast_ref as generic mux clk: mediatek: clk-mt8195-mfg: Reparent mfg_bg3d and propagate rate changes clk: mediatek: mt8183: Add clk mux notifier for MFG mux clk: mediatek: mux: add clk notifier functions clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent clk: mediatek: Use mtk_clk_register_gates_with_dev in simple probe clk: mediatek: gate: Export mtk_clk_register_gates_with_dev clk: mediatek: add VDOSYS1 clock dt-bindings: clk: mediatek: Add MT8195 DPI clocks ... * clk-rm: clk: davinci: remove PLL and PSC clocks for DaVinci DM644x and DM646x * clk-ast: clk: ast2600: BCLK comes from EPLL * clk-qcom: (97 commits) clk: qcom: gcc-sm6375: Ensure unsigned long type clk: qcom: gcc-sm6375: Remove unused variables clk: qcom: kpss-xcc: convert to parent data API clk: introduce (devm_)hw_register_mux_parent_data_table API clk: qcom: gcc-msm8939: use ARRAY_SIZE instead of specifying num_parents clk: qcom: gcc-msm8939: use parent_hws where possible dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml clk: qcom: gcc-sm6350: Update the .pwrsts for usb gdscs clk: qcom: gcc-sc8280xp: use retention for USB power domains clk: qcom: gdsc: add missing error handling dt-bindings: clocks: qcom,gcc-sc8280xp: Fix typos clk: qcom: Add global clock controller driver for SM6375 dt-bindings: clock: add SM6375 QCOM global clock bindings clk: qcom: alpha: Add support for programming the PLL_FSM_LEGACY_MODE bit clk: qcom: gcc-sc7280: Update the .pwrsts for usb gdscs clk: qcom: gcc-sc7180: Update the .pwrsts for usb gdsc clk: qcom: gdsc: Fix the handling of PWRSTS_RET support clk: qcom: Add SC8280XP GPU clock controller dt-bindings: clock: Add Qualcomm SC8280XP GPU binding clk: qcom: smd: Add SM6375 clocks ...

dt-bindings: clock: mediatek: add bindings for MT8365 SoC

2022-09-30T22:07:43Z

Add the clock bindings for the MediaTek MT8365 SoC. Signed-off-by: Fabien Parent Reviewed-by: Krzysztof Kozlowski Signed-off-by: Markus Schneider-Pargmann Link: https://lore.kernel.org/r/20220822152652.3499972-2-msp@baylibre.com Signed-off-by: Stephen Boyd

dt-bindings: marvell,pxa168: add clock ids for SDH AXI clocks

2022-09-30T20:34:07Z

These are clocks shared by SDH0/1 and SDH2/3, respectively. Signed-off-by: Doug Brown Link: https://lore.kernel.org/r/20220612192937.162952-12-doug@schmorgal.com Acked-by: Rob Herring Signed-off-by: Stephen Boyd

dt-bindings: marvell,pxa168: add clock id for SDH3

2022-09-30T20:34:06Z

There are four SDHC peripherals on the PXA168, but only three of them were present in the DT bindings. This commit adds the fourth. Signed-off-by: Doug Brown Link: https://lore.kernel.org/r/20220612192937.162952-10-doug@schmorgal.com Acked-by: Rob Herring Signed-off-by: Stephen Boyd

dt-bindings: marvell,pxa168: add clock ids for additional dividers

2022-09-30T20:34:06Z

This adds a few new clocks divided from PLL1 and CLK32 that are potentially used by a few peripherals with muxed clocks. Signed-off-by: Doug Brown Link: https://lore.kernel.org/r/20220612192937.162952-4-doug@schmorgal.com Acked-by: Rob Herring Signed-off-by: Stephen Boyd

dt-bindings: clock: add SM6375 QCOM global clock bindings

2022-09-28T03:25:57Z

Add device tree bindings for global clock controller for SM6375 SoCs. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220921001303.56151-2-konrad.dybcio@somainline.org

dt-bindings: clock: Add Qualcomm SC8280XP GPU binding

2022-09-27T17:07:30Z

Add compatible for the Qualcomm SC8280XP GPU. Signed-off-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220926173025.4747-2-quic_bjorande@quicinc.com