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<title>linux-dev/include/soc/nps, branch master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/include/soc/nps?h=master</id>
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<updated>2021-01-05T20:59:41Z</updated>
<entry>
<title>include/soc: remove headers for EZChip NPS</title>
<updated>2021-01-05T20:59:41Z</updated>
<author>
<name>Vineet Gupta</name>
<email>Vineet.Gupta1@synopsys.com</email>
</author>
<published>2020-11-05T21:22:10Z</published>
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<id>urn:sha1:f4d9359de8ac0fb64a5ecc9c34833705eb53327b</id>
<content type='text'>
NPS platform has been removed from ARC port and there are no in-tree
user of it now . So RIP !

Signed-off-by: Vineet Gupta &lt;vgupta@synopsys.com&gt;
</content>
</entry>
<entry>
<title>irqchip/eznps: Fix build error for !ARC700 builds</title>
<updated>2020-08-27T20:15:17Z</updated>
<author>
<name>Vineet Gupta</name>
<email>vgupta@synopsys.com</email>
</author>
<published>2020-08-24T19:10:33Z</published>
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<id>urn:sha1:89d29997f103d08264b0685796b420d911658b96</id>
<content type='text'>
eznps driver is supposed to be platform independent however it ends up
including stuff from inside arch/arc headers leading to rand config
build errors.

The quick hack to fix this (proper fix is too much chrun for non active
user-base) is to add following to nps platform agnostic header.
 - copy AUX_IENABLE from arch/arc header
 - move CTOP_AUX_IACK from arch/arc/plat-eznps/*/**

Reported-by: kernel test robot &lt;lkp@intel.com&gt;
Reported-by: Sebastian Andrzej Siewior &lt;bigeasy@linutronix.de&gt;
Link: https://lkml.kernel.org/r/20200824095831.5lpkmkafelnvlpi2@linutronix.de
Signed-off-by: Vineet Gupta &lt;vgupta@synopsys.com&gt;
</content>
</entry>
<entry>
<title>soc: Support for NPS HW scheduling</title>
<updated>2016-11-30T19:54:25Z</updated>
<author>
<name>Noam Camus</name>
<email>noamca@mellanox.com</email>
</author>
<published>2016-11-16T06:31:11Z</published>
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<id>urn:sha1:09dcd1958be42ea473fef24a2c02d975f520ea71</id>
<content type='text'>
This new header file is for NPS400 SoC (part of ARC architecture).
The header file includes macros for save/restore of HW scheduling.
The control of HW scheduling is achieved by writing core registers.
This code was moved from arc/plat-eznps so it can be used
from drivers/clocksource/, available only for CONFIG_EZNPS_MTM_EXT.

Signed-off-by: Noam Camus &lt;noamca@mellanox.com&gt;
Acked-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
</content>
</entry>
<entry>
<title>soc: Support for EZchip SoC</title>
<updated>2016-05-09T04:02:31Z</updated>
<author>
<name>Noam Camus</name>
<email>noamc@ezchip.com</email>
</author>
<published>2015-12-06T07:00:56Z</published>
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<id>urn:sha1:ebc326be87e5989a878872cd3e42cc0061458ab7</id>
<content type='text'>
This header file is for NPS400 SoC.
It includes macros for accessing memory mapped registers.
These are functional registers that core can use to configure SoC.

Signed-off-by: Noam Camus &lt;noamc@ezchip.com&gt;
Acked-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
Acked-by: Vineet Gupta &lt;vgupta@synopsys.com&gt;
</content>
</entry>
</feed>
