linux-dev/tools/perf/arch/x86/tests, branch master

perf tools: Do not pass NULL to parse_events()

2022-08-10T17:30:09Z

Many cases do not use the extra error information provided by parse_events and instead pass NULL as the struct parse_events_error pointer. Add a wrapper for those cases so that the pointer is never NULL. Signed-off-by: Adrian Hunter Cc: Ian Rogers Cc: Jiri Olsa Cc: Namhyung Kim Link: https://lore.kernel.org/r/20220809080702.6921-4-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo

perf test: Remove x86 rdpmc test

2022-08-01T12:18:12Z

This test has been superseded by test_stat_user_read in: tools/lib/perf/tests/test-evsel.c The updated test doesn't divide-by-0 when running time of a counter is 0. It also supports ARM64. Signed-off-by: Ian Rogers Acked-by: Rob Herring Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Anshuman Khandual Cc: Jiri Olsa Cc: Kajol Jain Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Stephane Eranian Link: http://lore.kernel.org/lkml/20220719223946.176299-3-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo

Merge remote-tracking branch 'torvalds/master' into perf/core

2022-03-22T20:52:10Z

To pick up fixes that went thru perf/urgent and now are fixed by an upcoming patch. Signed-off-by: Arnaldo Carvalho de Melo

perf intel-pt: pkt-decoder: Add MODE.Exec IFLAG bit

2022-02-15T20:06:11Z

As of Intel SDM (https://www.intel.com/sdm) version 076, there is a new Intel PT feature called Event Trace which adds a bit to the existing MODE.Exec packet to record the interrupt flag. Amend the packet decoder and packet decoder test accordingly. Signed-off-by: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Jiri Olsa Link: https://lore.kernel.org/r/20220124084201.2699795-5-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo

perf intel-pt: pkt-decoder: Add CFE and EVD packets

2022-02-15T20:05:44Z

As of Intel SDM (https://www.intel.com/sdm) version 076, there is a new Intel PT feature called Event Trace which requires 2 new packets CFE and EVD. Add them to the packet decoder and packet decoder test. Committer notes: I got the "Intel® 64 and IA-32 architectures software developer’s manual combined volumes: 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4" PDF at: https://cdrdv2.intel.com/v1/dl/getContent/671200 And these new packets are described in page 3951: 32.2.4 Event Trace is a capability that exposes details about the asynchronous events, when they are generated, and when their corresponding software event handler completes execution. These include: o Interrupts, including NMI and SMI, including the interrupt vector when defined. o Faults, exceptions including the fault vector. — Page faults additionally include the page fault address, when in context. o Event handler returns, including IRET and RSM. o VM exits and VM entries.¹ — VM exits include the values written to the “exit reason” and “exit qualification” VMCS fields. INIT and SIPI events. o TSX aborts, including the abort status returned for the RTM instructions. o Shutdown. Additionally, it provides indication of the status of the Interrupt Flag (IF), to indicate when interrupts are masked. Signed-off-by: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Jiri Olsa Link: https://lore.kernel.org/r/20220124084201.2699795-4-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo

perf intel-pt: pkt-decoder-test: Fix scope of test_data

2022-02-15T20:05:20Z

Make test_data 'static' otherwise it will conflict with any global variable of the same name. Signed-off-by: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Jiri Olsa Link: https://lore.kernel.org/r/20220124084201.2699795-2-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo

perf/tests: Add AVX512-FP16 instructions to x86 instruction decoder test

2022-01-23T19:37:57Z

perf/tests: Add misc instructions to the x86 instruction decoder test

2022-01-23T19:37:50Z

The x86 instruction decoder is used for both kernel instructions and user space instructions (e.g. uprobes, perf tools Intel PT), so it is good to update it with new instructions. Add the following instructions to the x86 instruction decoder test: User Interrupt clui senduipi stui testui uiret Prediction history reset hreset Serialize instruction execution serialize TSX suspend load address tracking xresldtrk xsusldtrk A subsequent patch adds the instructions to the instruction decoder. Reference: Intel Architecture Instruction Set Extensions and Future Features Programming Reference May 2021 Document Number: 319433-044 Example: $ perf test -v "x86 instruction decoder" |& grep -i hreset Failed to decode length (4 vs expected 6): f3 0f 3a f0 c0 00 hreset $0x0 Failed to decode length (4 vs expected 6): f3 0f 3a f0 c0 00 hreset $0x0 Signed-off-by: Adrian Hunter Signed-off-by: Borislav Petkov Acked-by: Arnaldo Carvalho de Melo Acked-by: Masami Hiramatsu Link: https://lore.kernel.org/r/20211202095029.2165714-4-adrian.hunter@intel.com

perf/tests: Add AMX instructions to x86 instruction decoder test

2022-01-23T19:37:42Z

The x86 instruction decoder is used for both kernel instructions and user space instructions (e.g. uprobes, perf tools Intel PT), so it is good to update it with new instructions. Add AMX instructions to the x86 instruction decoder test. A subsequent patch adds the instructions to the instruction decoder. Reference: Intel Architecture Instruction Set Extensions and Future Features Programming Reference May 2021 Document Number: 319433-044 Example: $ INSN='ldtilecfg\|sttilecfg\|tdpbf16ps\|tdpbssd\|' $ INSN+='tdpbsud\|tdpbusd\|'tdpbuud\|tileloadd\|' $ INSN+='tileloaddt1\|tilerelease\|tilestored\|tilezero' $ perf test -v "x86 instruction decoder" |& grep -i $INSN Failed to decode: c4 e2 78 49 04 c8 ldtilecfg (%rax,%rcx,8) Failed to decode: c4 c2 78 49 04 c8 ldtilecfg (%r8,%rcx,8) Failed to decode: c4 e2 79 49 04 c8 sttilecfg (%rax,%rcx,8) Failed to decode: c4 c2 79 49 04 c8 sttilecfg (%r8,%rcx,8) Failed to decode: c4 e2 7a 5c d1 tdpbf16ps %tmm0,%tmm1,%tmm2 Failed to decode: c4 e2 7b 5e d1 tdpbssd %tmm0,%tmm1,%tmm2 Failed to decode: c4 e2 7a 5e d1 tdpbsud %tmm0,%tmm1,%tmm2 Failed to decode: c4 e2 79 5e d1 tdpbusd %tmm0,%tmm1,%tmm2 Failed to decode: c4 e2 78 5e d1 tdpbuud %tmm0,%tmm1,%tmm2 Failed to decode: c4 e2 7b 4b 0c c8 tileloadd (%rax,%rcx,8),%tmm1 Failed to decode: c4 c2 7b 4b 14 c8 tileloadd (%r8,%rcx,8),%tmm2 Failed to decode: c4 e2 79 4b 0c c8 tileloaddt1 (%rax,%rcx,8),%tmm1 Failed to decode: c4 c2 79 4b 14 c8 tileloaddt1 (%r8,%rcx,8),%tmm2 Failed to decode: c4 e2 78 49 c0 tilerelease Failed to decode: c4 e2 7a 4b 0c c8 tilestored %tmm1,(%rax,%rcx,8) Failed to decode: c4 c2 7a 4b 14 c8 tilestored %tmm2,(%r8,%rcx,8) Failed to decode: c4 e2 7b 49 c0 tilezero %tmm0 Failed to decode: c4 e2 7b 49 f8 tilezero %tmm7 Signed-off-by: Adrian Hunter Signed-off-by: Borislav Petkov Acked-by: Arnaldo Carvalho de Melo Acked-by: Masami Hiramatsu Link: https://lore.kernel.org/r/20211202095029.2165714-2-adrian.hunter@intel.com

perf test: Rename struct test to test_suite

2021-11-13T13:32:22Z

This is to align with kunit's terminology. Signed-off-by: Ian Rogers Tested-by: Sohaib Mohamed Acked-by: Jiri Olsa Cc: Alexander Shishkin Cc: Brendan Higgins Cc: Daniel Latypov Cc: David Gow Cc: Ingo Molnar Cc: Jin Yao Cc: John Garry Cc: Mark Rutland Cc: Namhyung Kim Cc: Paul Clarke Cc: Peter Zijlstra Cc: Stephane Eranian Link: https://lore.kernel.org/r/20211104064208.3156807-6-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo