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<title>linux-dev/tools/testing/selftests/kvm/include/riscv, branch linus/master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/tools/testing/selftests/kvm/include/riscv?h=linus%2Fmaster</id>
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<updated>2022-05-20T03:38:56Z</updated>
<entry>
<title>KVM: selftests: riscv: Improve unexpected guest trap handling</title>
<updated>2022-05-20T03:38:56Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-04-09T04:32:36Z</published>
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<id>urn:sha1:ac6c85e962d4c009c499d93657f25f46fd8212b9</id>
<content type='text'>
Currently, we simply hang using "while (1) ;" upon any unexpected
guest traps because the default guest trap handler is guest_hang().

The above approach is not useful to anyone because KVM selftests
users will only see a hung application upon any unexpected guest
trap.

This patch improves unexpected guest trap handling for KVM RISC-V
selftests by doing the following:
1) Return to host user-space
2) Dump VCPU registers
3) Die using TEST_ASSERT(0, ...)

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Tested-by: Mayuresh Chitale &lt;mchitale@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>KVM: selftests: riscv: Set PTE A and D bits in VS-stage page table</title>
<updated>2022-04-09T03:45:44Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-04-09T03:45:44Z</published>
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<id>urn:sha1:fac3725364397f9a40a101f089b86ea655a58d06</id>
<content type='text'>
Supporting hardware updates of PTE A and D bits is optional for any
RISC-V implementation so current software strategy is to always set
these bits in both G-stage (hypervisor) and VS-stage (guest kernel).

If PTE A and D bits are not set by software (hypervisor or guest)
then RISC-V implementations not supporting hardware updates of these
bits will cause traps even for perfectly valid PTEs.

Based on above explanation, the VS-stage page table created by various
KVM selftest applications is not correct because PTE A and D bits are
not set. This patch fixes VS-stage page table programming of PTE A and
D bits for KVM selftests.

Fixes: 3e06cdf10520 ("KVM: selftests: Add initial support for RISC-V
64-bit")
Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Tested-by: Mayuresh Chitale &lt;mchitale@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>KVM: selftests: Add initial support for RISC-V 64-bit</title>
<updated>2022-01-06T09:47:50Z</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2021-10-05T12:39:56Z</published>
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<id>urn:sha1:3e06cdf10520e629e711b76b21070d6e67ae7d06</id>
<content type='text'>
We add initial support for RISC-V 64-bit in KVM selftests using
which we can cross-compile and run arch independent tests such as:
demand_paging_test
dirty_log_test
kvm_create_max_vcpus,
kvm_page_table_test
set_memory_region_test
kvm_binary_stats_test

All VM guest modes defined in kvm_util.h require at least 48-bit
guest virtual address so to use KVM RISC-V selftests hardware
need to support at least Sv48 MMU for guest (i.e. VS-mode).

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-and-tested-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
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