linux-dev/tools/testing/selftests/powerpc/pmu, branch master

selftests/powerpc: Update bhrb filter sampling test for multiple branch filters

2022-09-28T09:22:13Z

For PERF_SAMPLE_BRANCH_STACK sample type, different branch_sample_type, ie branch filters are supported. The testcase "bhrb_filter_map_test" tests the valid and invalid filter maps in different powerpc platforms. Update this testcase to include scenario to cover multiple branch filters at sametime. Since powerpc doesn't support multiple filters at sametime, expect failure during perf_event_open. Reported-by: Disha Goel Signed-off-by: Athira Rajeev Reviewed-by: Kajol Jain Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220921145255.20972-3-atrajeev@linux.vnet.ibm.com

selftests/powerpc: Add missing PMU selftests to .gitignores

2022-08-15T10:59:17Z

Some recently added selftests don't have their binaries in .gitignores, so add them. I also alphabetically sorted sampling_tests/.gitignore while I was in there. Signed-off-by: Russell Currey Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220812071632.56095-1-ruscur@russell.cc

selftests/powerpc: Avoid GCC 12 uninitialised variable warning

2022-08-01T12:21:18Z

GCC 12 thinks that `actual` might be used uninitialised. It's not, the use is guarded by `bad_mmcr2` which is only set to true at the same point where `actual` is initialised. cycles_with_mmcr2_test.c: In function ‘cycles_with_mmcr2’: cycles_with_mmcr2_test.c:81:17: error: ‘actual’ may be used uninitialized [-Werror=maybe-uninitialized] 81 | printf("Bad MMCR2 value seen is 0x%lx\n", actual); Silence the warning by initialising `actual` to zero. Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220801113746.802046-1-mpe@ellerman.id.au

selftests/powerpc: Add missing files to .gitignores

2022-06-29T09:37:04Z

These were missed when the respective tests were added, add them now. Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220616070705.1941829-1-mpe@ellerman.id.au

selftests/powerpc/pmu: Add test for hardware cache events

2022-06-28T22:57:45Z

The testcase checks if the transalation of a generic hardware cache event is done properly via perf interface. The hardware cache events has type as PERF_TYPE_HW_CACHE and each event points to raw event code id. Testcase checks different combination of cache level, cache event operation type and cache event result type and verify for a given event code, whether transalation matches with the current cache event mappings via perf interface. Signed-off-by: Kajol Jain Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220610134113.62991-36-atrajeev@linux.vnet.ibm.com

selftests/powerpc/pmu: Add selftest for group constraint check for MMCRA thresh_sel field

2022-06-28T22:57:45Z

Thresh select bits in the event code is used to program thresh_sel field in Monitor Mode Control Register A (MMCRA: 45-47). When scheduling events as a group, all events in that group should match value in these bits. Otherwise event open for the sibling events will fail. Testcase uses event code PM_MRK_INST_CMPL (0x401e0) as leader and another event PM_THRESH_MET (0x101ec) as sibling event, and checks if group constraint checks for thresh_sel field added correctly via perf interface. Signed-off-by: Kajol Jain Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220610134113.62991-35-atrajeev@linux.vnet.ibm.com

selftests/powerpc/pmu: Add selftest for group constraint check for MMCRA thresh_ctl field

2022-06-28T22:57:45Z

Thresh control bits in the event code is used to program thresh_ctl field in Monitor Mode Control Register A (MMCRA: 48-55). When scheduling events as a group, all events in that group should match value in these bits. Otherwise event open for the sibling events will fail. Testcase uses event code PM_MRK_INST_CMPL (0x401e0) as leader and another event PM_THRESH_MET (101ec) as sibling event, and checks if group constraint checks for thresh_ctl field added correctly via perf interface. Signed-off-by: Kajol Jain Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220610134113.62991-34-atrajeev@linux.vnet.ibm.com

selftests/powerpc/pmu: Add selftest for group constraint for unit and pmc field in p9

2022-06-28T22:57:45Z

Unit and pmu bits in the event code is used to program unit and pmc fields in Monitor Mode Control Register 1 (MMCR1). For power9 platform, incase unit field value is within 6 to 9, one of the event in the group should use PMC4. Otherwise event_open should fail for that group. Signed-off-by: Kajol Jain Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220610134113.62991-33-atrajeev@linux.vnet.ibm.com

selftests/powerpc/pmu: Add selftest for group constraint check for MMCRA thresh_cmp field

2022-06-28T22:57:45Z

Thresh compare bits for a event is used to program thresh compare field in Monitor Mode Control Register A (MMCRA: 9-18 bits for power9 and MMCRA: 8-18 bits for power10). When scheduling events as a group, all events in that group should match value in thresh compare bits. Otherwise event open for the sibling events will fail. Testcase uses event code "0x401e0" as leader and another event "0x101ec" as sibling event, and checks for thresh compare constraint via perf interface. Signed-off-by: Kajol Jain Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220610134113.62991-32-atrajeev@linux.vnet.ibm.com

selftests/powerpc/pmu: Add selftest for group constraint check for MMCR1 cache bits

2022-06-28T22:57:44Z

Data and instruction cache qualifier bits in the event code is used to program cache select field in Monitor Mode Control Register 1 (MMCR1: 16-17). When scheduling events as a group, all events in that group should match value in these bits. Otherwise event open for the sibling events will fail. Testcase uses event code "0x1100fc" as leader and other events like "0x23e054" and "0x13e054" as sibling events to checks for l1 cache select field constraints via perf interface. Signed-off-by: Kajol Jain Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220610134113.62991-31-atrajeev@linux.vnet.ibm.com