linux-dev/tools/testing/selftests/powerpc/ptrace, branch master

selftests/powerpc/ptrace: Add peek/poke of FPRs

2022-07-25T02:05:16Z

Currently the ptrace-gpr test only tests the GET/SET(FP)REGS ptrace APIs. But there's an alternate (older) API, called PEEK/POKEUSR. Add some minimal testing of PEEK/POKEUSR of the FPRs. This is sufficient to detect the bug that was fixed recently in the 32-bit ptrace FPR handling. Depends-on: 8e1278444446 ("powerpc/32: Fix overread/overwrite of thread_struct via ptrace") Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220627140239.2464900-13-mpe@ellerman.id.au

selftests/powerpc/ptrace: Use more interesting values

2022-07-25T02:05:16Z

The ptrace-gpr test uses fixed values to test that registers can be read/written via ptrace. In particular it sets all GPRs to 1, which means the test could miss some types of bugs - eg. if the kernel was only returning the low word. So generate some random values at startup and use those instead. Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220627140239.2464900-12-mpe@ellerman.id.au

selftests/powerpc/ptrace: Make child errors more obvious

2022-07-25T02:05:16Z

Use the FAIL_IF() macro so that errors in the child report a line number, rather than just silently exiting. Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220627140239.2464900-11-mpe@ellerman.id.au

selftests/powerpc/ptrace: Do more of ptrace-gpr in asm

2022-07-25T02:05:16Z

The ptrace-gpr test includes some inline asm to load GPR and FPR registers. It then goes back to C to wait for the parent to trace it and then checks register contents. The split between inline asm and C is fragile, it relies on the compiler not using any non-volatile GPRs after the inline asm block. It also requires a very large and unwieldy inline asm block. So convert the logic to set registers, wait, and store registers to a single asm function, meaning there's no window for the compiler to intervene. Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220627140239.2464900-10-mpe@ellerman.id.au

selftests/powerpc/ptrace: Build the ptrace-gpr test as 32-bit when possible

2022-07-25T02:05:16Z

The ptrace-gpr test can now be built 32-bit, so do that if that's the compiler default rather than forcing a 64-bit build. Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220627140239.2464900-9-mpe@ellerman.id.au

selftests/powerpc/ptrace: Convert to load/store doubles

2022-07-25T02:05:16Z

Some of the ptrace tests check the contents of floating pointer registers. Currently these use float, which is always 4 bytes, but the ptrace API supports saving/restoring 8 bytes per register, so switch to using doubles to exercise the code more fully. Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220627140239.2464900-8-mpe@ellerman.id.au

selftests/powerpc/ptrace: Split CFLAGS better

2022-07-25T02:05:15Z

Currently all ptrace tests are built 64-bit and with TM enabled. Only the TM tests need TM enabled, so split those out into a separate variable so that can be specified precisely. Split the rest of the tests into a variable, and add -m64 to CFLAGS for those tests, so that in a subsequent patch some tests can be made to build 32-bit. Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220627140239.2464900-3-mpe@ellerman.id.au

selftests/powerpc/ptrace: Set LOCAL_HDRS

2022-07-25T02:05:15Z

Set LOCAL_HDRS so header changes cause rebuilds. The lib.mk logic adds all the headers in LOCAL_HDRS as dependencies, so there's no need to also list them explicitly. Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20220627140239.2464900-2-mpe@ellerman.id.au

selftests: Skip TM tests on synthetic TM implementations

2021-08-26T11:21:06Z

Transactional Memory was removed from the architecture in ISA v3.1. For threads running in P8/P9 compatibility mode on P10 a synthetic TM implementation is provided. In this implementation, tbegin. always sets cr0 eq meaning the abort handler is always called. This is not an issue as users of TM are expected to have a fallback non transactional way to make forward progress in the abort handler. The TEXASR indicates if a transaction failure is due to a synthetic implementation. Some of the TM self tests need a non-degenerate TM implementation for their testing to be meaningful so check for a synthetic implementation and skip the test if so. Signed-off-by: Jordan Niethe Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20210729041317.366612-2-jniethe5@gmail.com

selftests/powerpc: Add missing clobbered register to to ptrace TM tests

2021-08-26T11:21:06Z

ISA v3.1 removes TM but includes a synthetic implementation for backwards compatibility. With this implementation, the tests ptrace-tm-spd-gpr and ptrace-tm-gpr should never be able to make any forward progress and eventually should be killed by the timeout. Instead on a P10 running in P9 mode, ptrace_tm_gpr fails like so: test: ptrace_tm_gpr tags: git_version:unknown Starting the child ... ... GPR[27]: 1 Expected: 2 GPR[28]: 1 Expected: 2 GPR[29]: 1 Expected: 2 GPR[30]: 1 Expected: 2 GPR[31]: 1 Expected: 2 [FAIL] Test FAILED on line 98 failure: ptrace_tm_gpr selftests: ptrace-tm-gpr [FAIL] The problem is in the inline assembly of the child. r0 is loaded with a value in the child's transaction abort handler but this register is not included in the clobbers list. This means it is possible that this statement: cptr[1] = 0; which is meant to signal the parent to wait may actually use the value placed into r0 by the inline assembly incorrectly signal the parent to continue. By inspection the same problem is present in ptrace-tm-spd-gpr. Adding r0 to the clobbbers list makes the test fail correctly via a timeout on a P10 running in P8/P9 compatibility mode. Suggested-by: Michael Neuling Signed-off-by: Jordan Niethe Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20210729041317.366612-1-jniethe5@gmail.com