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authorBoyuan Zhang <boyuan.zhang@amd.com>2020-07-01 17:57:47 -0400
committerAlex Deucher <alexander.deucher@amd.com>2020-07-15 12:47:12 -0400
commitebb06097ee29442461f9b3bcd745d85e6fa9996b (patch)
tree4ad10274c7599242f0a990a8b1ced89d0b150770
parentdrm/amdgpu: enable cp_fw_write_wait for navy_flounder (diff)
downloadlinux-dev-ebb06097ee29442461f9b3bcd745d85e6fa9996b.tar.xz
linux-dev-ebb06097ee29442461f9b3bcd745d85e6fa9996b.zip
drm/amdgpu: enable VCN3.0 PG and CG for navy_flounder
Enable VCN3.0 PG and CG for navy_flounder by setting up the flags to the ASIC Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to '')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/nv.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 5e03e3c59aae..13efe87c7a75 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -775,8 +775,8 @@ static int nv_common_early_init(void *handle)
adev->external_rev_id = adev->rev_id + 0x28;
break;
case CHIP_NAVY_FLOUNDER:
- adev->cg_flags = 0;
- adev->pg_flags = 0;
+ adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG;
+ adev->pg_flags = AMD_PG_SUPPORT_VCN;
adev->external_rev_id = adev->rev_id + 0x32;
break;