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authorImre Deak <imre.deak@intel.com>2015-03-10 21:18:30 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-04-16 09:20:15 +0200
commiteee215660cedb4ee3c93de52a9bbc742891bb290 (patch)
tree6d818ae2383ba813ba8d01628cddc44c7fcaf956
parentdrm/i915/bxt: add display initialize/uninitialize sequence (PHY) (diff)
downloadlinux-dev-eee215660cedb4ee3c93de52a9bbc742891bb290.tar.xz
linux-dev-eee215660cedb4ee3c93de52a9bbc742891bb290.zip
drm/i915/bxt: add description about the BXT PHYs
Extend the VLV/CHV DPIO (PHY) documentation with the BXT specifics. v2: - add more detail about the mapping between ports and transcoders (ville) Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--Documentation/DocBook/drm.tmpl4
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h18
2 files changed, 14 insertions, 8 deletions
diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
index f4976cd7b32b..a8509c2b9c17 100644
--- a/Documentation/DocBook/drm.tmpl
+++ b/Documentation/DocBook/drm.tmpl
@@ -4067,7 +4067,7 @@ int num_ioctls;</synopsis>
<title>DPIO</title>
!Pdrivers/gpu/drm/i915/i915_reg.h DPIO
<table id="dpiox2">
- <title>Dual channel PHY (VLV/CHV)</title>
+ <title>Dual channel PHY (VLV/CHV/BXT)</title>
<tgroup cols="8">
<colspec colname="c0" />
<colspec colname="c1" />
@@ -4118,7 +4118,7 @@ int num_ioctls;</synopsis>
</tgroup>
</table>
<table id="dpiox1">
- <title>Single channel PHY (CHV)</title>
+ <title>Single channel PHY (CHV/BXT)</title>
<tgroup cols="4">
<colspec colname="c0" />
<colspec colname="c1" />
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6e0913db6e24..11b9a0898111 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -715,7 +715,7 @@ enum skl_disp_power_wells {
/**
* DOC: DPIO
*
- * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI
+ * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
* ports. DPIO is the name given to such a display PHY. These PHYs
* don't follow the standard programming model using direct MMIO
* registers, and instead their registers must be accessed trough IOSF
@@ -746,7 +746,7 @@ enum skl_disp_power_wells {
* controlled from the display controller side. No DPIO registers
* need to be accessed during AUX communication,
*
- * Generally the common lane corresponds to the pipe and
+ * Generally on VLV/CHV the common lane corresponds to the pipe and
* the spline (PCS/TX) corresponds to the port.
*
* For dual channel PHY (VLV/CHV):
@@ -768,11 +768,17 @@ enum skl_disp_power_wells {
*
* port D == PCS/TX CH0
*
- * Note: digital port B is DDI0, digital port C is DDI1,
- * digital port D is DDI2
+ * On BXT the entire PHY channel corresponds to the port. That means
+ * the PLL is also now associated with the port rather than the pipe,
+ * and so the clock needs to be routed to the appropriate transcoder.
+ * Port A PLL is directly connected to transcoder EDP and port B/C
+ * PLLs can be routed to any transcoder A/B/C.
+ *
+ * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
+ * digital port D (CHV) or port A (BXT).
*/
/*
- * Dual channel PHY (VLV/CHV)
+ * Dual channel PHY (VLV/CHV/BXT)
* ---------------------------------
* | CH0 | CH1 |
* | CMN/PLL/REF | CMN/PLL/REF |
@@ -784,7 +790,7 @@ enum skl_disp_power_wells {
* | DDI0 | DDI1 | DP/HDMI ports
* ---------------------------------
*
- * Single channel PHY (CHV)
+ * Single channel PHY (CHV/BXT)
* -----------------
* | CH0 |
* | CMN/PLL/REF |