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authorCatalin Marinas <catalin.marinas@arm.com>2009-04-30 17:06:15 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-04-30 20:12:59 +0100
commit855c551f5b8cc3815d58e1056c1f1e7c461e2d24 (patch)
treec2a84666b3a86c3e5cb5272ed42b802f9411ec33
parent[ARM] 5487/1: ARM errata: Stale prediction on replaced interworking branch (diff)
downloadlinux-dev-855c551f5b8cc3815d58e1056c1f1e7c461e2d24.tar.xz
linux-dev-855c551f5b8cc3815d58e1056c1f1e7c461e2d24.zip
[ARM] 5490/1: ARM errata: Processor deadlock when a false hazard is created
This patch adds a workaround for the 458693 Cortex-A8 (r2p0) erratum. It sets the corresponding bits in the auxiliary control register so that the PLD instruction becomes a NOP. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--arch/arm/Kconfig13
-rw-r--r--arch/arm/mm/proc-v7.S6
2 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 84e4816362b3..49f85664083d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -765,6 +765,19 @@ config ARM_ERRATA_430973
Note that setting specific bits in the ACTLR register may not be
available in non-secure mode.
+config ARM_ERRATA_458693
+ bool "ARM errata: Processor deadlock when a false hazard is created"
+ depends on CPU_V7
+ help
+ This option enables the workaround for the 458693 Cortex-A8 (r2p0)
+ erratum. For very specific sequences of memory operations, it is
+ possible for a hazard condition intended for a cache line to instead
+ be incorrectly associated with a different cache line. This false
+ hazard might then cause a processor deadlock. The workaround enables
+ the L1 caching of the NEON accesses and disables the PLD instruction
+ in the ACTLR register. Note that setting specific bits in the ACTLR
+ register may not be available in non-secure mode.
+
endmenu
source "arch/arm/common/Kconfig"
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index fc81159596fe..370baa7a0f08 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -188,6 +188,12 @@ __v7_setup:
orr r10, r10, #(1 << 6) @ set IBE to 1
mcr p15, 0, r10, c1, c0, 1 @ write aux control register
#endif
+#ifdef CONFIG_ARM_ERRATA_458693
+ mrc p15, 0, r10, c1, c0, 1 @ read aux control register
+ orr r10, r10, #(1 << 5) @ set L1NEON to 1
+ orr r10, r10, #(1 << 9) @ set PLDNOP to 1
+ mcr p15, 0, r10, c1, c0, 1 @ write aux control register
+#endif
mov r10, #0
#ifdef HARVARD_CACHE
mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate