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authorJouni Malinen <jouni.malinen@atheros.com>2011-02-04 13:51:28 +0200
committerJohn W. Linville <linville@tuxdriver.com>2011-02-04 16:29:52 -0500
commit8e5461041f4498e3c8f4e0a51187f608f0a18b08 (patch)
tree1b8fc4eaf6031dc1ea7b70a2d10011916586196f
parentmac80211: do not restart ps timer during scan or offchannel (diff)
downloadlinux-dev-8e5461041f4498e3c8f4e0a51187f608f0a18b08.tar.xz
linux-dev-8e5461041f4498e3c8f4e0a51187f608f0a18b08.zip
ath: Fix clearing of secondary key cache entry for TKIP
All register writes to the key cache have to be done in pairs. However, the clearing of a separate MIC entry with hardware revisions that use combined MIC key layout did not do that with one of the registers. Add the matching register write to the following register to make the KEY4 register write actually complete. This is mostly a fix for a theoretical issue since the incorrect entry that could potentially be left behind in the key cache would not match with received frames. Anyway, better make this code clean the entry correctly using paired register writes. Signed-off-by: Jouni Malinen <jouni.malinen@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r--drivers/net/wireless/ath/key.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/net/wireless/ath/key.c b/drivers/net/wireless/ath/key.c
index 5d465e5fcf24..37b8e115375a 100644
--- a/drivers/net/wireless/ath/key.c
+++ b/drivers/net/wireless/ath/key.c
@@ -58,8 +58,11 @@ bool ath_hw_keyreset(struct ath_common *common, u16 entry)
REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
- if (common->crypt_caps & ATH_CRYPT_CAP_MIC_COMBINED)
+ if (common->crypt_caps & ATH_CRYPT_CAP_MIC_COMBINED) {
REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
+ REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
+ AR_KEYTABLE_TYPE_CLR);
+ }
}