diff options
| author |   Mark Brown <broonie@kernel.org> | 2021-04-12 16:19:53 +0100 |
|---|---|---|
| committer |   Catalin Marinas <catalin.marinas@arm.com> | 2021-04-30 18:53:42 +0100 |
| commit | ee61f36d3e46bdb1c8910d1bd5c0863130c7b951 (patch) | |
| tree | 57aebfb36ec13b722203080f440789e6ff97359a /Documentation/arm64/booting.rst | |
| parent | arm64: cpufeatures: use min and max (diff) | |
| download | linux-dev-ee61f36d3e46bdb1c8910d1bd5c0863130c7b951.tar.xz linux-dev-ee61f36d3e46bdb1c8910d1bd5c0863130c7b951.zip | |
arm64: Relax booting requirements for configuration of traps
Currently we require that a number of system registers be configured to
disable traps when starting the kernel. Add an explicit note that the
requirement is that the system behave as if the traps are disabled so
transparent handling of the traps is fine, this should be implicit for
people familiar with working with standards documents but it doesn't hurt
to be explicit.
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20210412151955.16078-2-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to '')
| -rw-r--r-- | Documentation/arm64/booting.rst | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst index 4fcc00add117..b21049ab6c69 100644 --- a/Documentation/arm64/booting.rst +++ b/Documentation/arm64/booting.rst @@ -279,7 +279,10 @@ Before jumping into the kernel, the following conditions must be met: The requirements described above for CPU mode, caches, MMUs, architected timers, coherency and system registers apply to all CPUs. All CPUs must -enter the kernel in the same exception level. +enter the kernel in the same exception level. Where the values documented +disable traps it is permissible for these traps to be enabled so long as +those traps are handled transparently by higher exception levels as though +the values documented were set. The boot loader is expected to enter the kernel on each CPU in the following manner: |