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authorRich Wiley <rwiley@nvidia.com>2021-03-23 17:28:09 -0700
committerWill Deacon <will@kernel.org>2021-03-25 10:00:23 +0000
commit20109a859a9b514eb10c22b8a14b5704ffe93897 (patch)
treecb12010828a5ed3a781337e3a5048140209353e8 /Documentation/arm64
parentarm64/process.c: fix Wmissing-prototypes build warnings (diff)
downloadlinux-dev-20109a859a9b514eb10c22b8a14b5704ffe93897.tar.xz
linux-dev-20109a859a9b514eb10c22b8a14b5704ffe93897.zip
arm64: kernel: disable CNP on Carmel
On NVIDIA Carmel cores, CNP behaves differently than it does on standard ARM cores. On Carmel, if two cores have CNP enabled and share an L2 TLB entry created by core0 for a specific ASID, a non-shareable TLBI from core1 may still see the shared entry. On standard ARM cores, that TLBI will invalidate the shared entry as well. This causes issues with patchsets that attempt to do local TLBIs based on cpumasks instead of broadcast TLBIs. Avoid these issues by disabling CNP support for NVIDIA Carmel cores. Signed-off-by: Rich Wiley <rwiley@nvidia.com> Link: https://lore.kernel.org/r/20210324002809.30271-1-rwiley@nvidia.com [will: Fix pre-existing whitespace issue] Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'Documentation/arm64')
-rw-r--r--Documentation/arm64/silicon-errata.rst3
1 files changed, 3 insertions, 0 deletions
diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
index 719510247292..d410a47ffa57 100644
--- a/Documentation/arm64/silicon-errata.rst
+++ b/Documentation/arm64/silicon-errata.rst
@@ -130,6 +130,9 @@ stable kernels.
| Marvell | ARM-MMU-500 | #582743 | N/A |
+----------------+-----------------+-----------------+-----------------------------+
+----------------+-----------------+-----------------+-----------------------------+
+| NVIDIA | Carmel Core | N/A | NVIDIA_CARMEL_CNP_ERRATUM |
++----------------+-----------------+-----------------+-----------------------------+
++----------------+-----------------+-----------------+-----------------------------+
| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
+----------------+-----------------+-----------------+-----------------------------+
+----------------+-----------------+-----------------+-----------------------------+