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authorWill Deacon <will@kernel.org>2021-10-29 12:24:59 +0100
committerWill Deacon <will@kernel.org>2021-10-29 12:24:59 +0100
commit2bc655ce29422b94fcb4c9710d12664195897e42 (patch)
tree7f5de5ec76e860b3ebac9a71dac929d0a046ad6d /Documentation/arm64
parentMerge branch 'for-next/kselftest' into for-next/core (diff)
parentarm64: Select POSIX_CPU_TIMERS_TASK_WORK (diff)
downloadlinux-dev-2bc655ce29422b94fcb4c9710d12664195897e42.tar.xz
linux-dev-2bc655ce29422b94fcb4c9710d12664195897e42.zip
Merge branch 'for-next/misc' into for-next/core
* for-next/misc: arm64: Select POSIX_CPU_TIMERS_TASK_WORK arm64: Document boot requirements for FEAT_SME_FA64 arm64: ftrace: use function_nocfi for _mcount as well arm64: asm: setup.h: export common variables arm64/traps: Avoid unnecessary kernel/user pointer conversion
Diffstat (limited to 'Documentation/arm64')
-rw-r--r--Documentation/arm64/booting.rst10
1 files changed, 10 insertions, 0 deletions
diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst
index 3f9d86557c5e..52d060caf8bb 100644
--- a/Documentation/arm64/booting.rst
+++ b/Documentation/arm64/booting.rst
@@ -340,6 +340,16 @@ Before jumping into the kernel, the following conditions must be met:
- SMCR_EL2.LEN must be initialised to the same value for all CPUs the
kernel will execute on.
+ For CPUs with the Scalable Matrix Extension FA64 feature (FEAT_SME_FA64)
+
+ - If EL3 is present:
+
+ - SMCR_EL3.FA64 (bit 31) must be initialised to 0b1.
+
+ - If the kernel is entered at EL1 and EL2 is present:
+
+ - SMCR_EL2.FA64 (bit 31) must be initialised to 0b1.
+
The requirements described above for CPU mode, caches, MMUs, architected
timers, coherency and system registers apply to all CPUs. All CPUs must
enter the kernel in the same exception level. Where the values documented