path: root/Documentation/arm64
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authorMark Brown <broonie@kernel.org>2021-04-01 19:09:39 +0100
committerCatalin Marinas <catalin.marinas@arm.com>2021-04-08 18:39:17 +0100
commit3e237387bb76cbbd254e82fb1e996e2f3af9e6a7 (patch)
treeb40acfe95ef55893cdc01f1744157648dc2722f9 /Documentation/arm64
parentLinux 5.12-rc3 (diff)
arm64: Document requirements for fine grained traps at boot
The arm64 FEAT_FGT extension introduces a set of traps to EL2 for accesses to small sets of registers and instructions from EL1 and EL0, access to which is controlled by EL3. Require access to it so that it is available to us in future and so that we can ensure these traps are disabled during boot. Signed-off-by: Mark Brown <broonie@kernel.org> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210401180942.35815-2-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'Documentation/arm64')
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst
index 7552dbc1cc54..92ec0bea1af5 100644
--- a/Documentation/arm64/booting.rst
+++ b/Documentation/arm64/booting.rst
@@ -270,6 +270,12 @@ Before jumping into the kernel, the following conditions must be met:
having 0b1 set for the corresponding bit for each of the auxiliary
counters present.
+ For CPUs with the Fine Grained Traps (FEAT_FGT) extension present:
+ - If EL3 is present and the kernel is entered at EL2:
+ - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
The requirements described above for CPU mode, caches, MMUs, architected
timers, coherency and system registers apply to all CPUs. All CPUs must
enter the kernel in the same exception level.