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authorMark Brown <broonie@kernel.org>2021-04-12 16:19:54 +0100
committerCatalin Marinas <catalin.marinas@arm.com>2021-04-30 18:53:43 +0100
commitb30dbf4d936224f83a98bea2328ff09e644a25b2 (patch)
tree6b1c0134d8360f7ac3f4784e89a2d3241300dc50 /Documentation/arm64
parentarm64: Relax booting requirements for configuration of traps (diff)
downloadlinux-dev-b30dbf4d936224f83a98bea2328ff09e644a25b2.tar.xz
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arm64: Explicitly require that FPSIMD instructions do not trap
We do not explicitly require that systems with FPSIMD support and EL3 have disabled EL3 traps when the kernel is started, while it is unlikely that systems will get this wrong for the sake of completeness let's spell it out. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20210412151955.16078-3-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'Documentation/arm64')
-rw-r--r--Documentation/arm64/booting.rst10
1 files changed, 10 insertions, 0 deletions
diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst
index b21049ab6c69..4d0e323c0a35 100644
--- a/Documentation/arm64/booting.rst
+++ b/Documentation/arm64/booting.rst
@@ -277,6 +277,16 @@ Before jumping into the kernel, the following conditions must be met:
- SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
+ For CPUs with Advanced SIMD and floating point support:
+
+ - If EL3 is present:
+
+ - CPTR_EL3.TFP (bit 10) must be initialised to 0b0.
+
+ - If EL2 is present and the kernel is entered at EL1:
+
+ - CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
+
The requirements described above for CPU mode, caches, MMUs, architected
timers, coherency and system registers apply to all CPUs. All CPUs must
enter the kernel in the same exception level. Where the values documented