path: root/Documentation/arm64
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authorMark Brown <broonie@kernel.org>2021-04-12 16:19:55 +0100
committerCatalin Marinas <catalin.marinas@arm.com>2021-04-30 18:53:43 +0100
commitff1c42cdfbcfba4cc75f3e21ed819ded2dad5f3e (patch)
tree571d1ba3bf35f1aeecbd3492e2dc74330f1aab40 /Documentation/arm64
parentarm64: Explicitly require that FPSIMD instructions do not trap (diff)
arm64: Explicitly document boot requirements for SVE
We do not currently document the requirements for configuration of the SVE system registers when booting the kernel, let's do so for completeness. We don't have a hard requirement that the vector lengths configured on different CPUs on initial boot be consistent since we have logic to constrain to the minimum supported value but we will reject any late CPUs which can't support the current maximum and introducing the concept of late CPUs seemed more complex than was useful so we require that all CPUs use the same value. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20210412151955.16078-4-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'Documentation/arm64')
1 files changed, 18 insertions, 0 deletions
diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst
index 4d0e323c0a35..18b8cc1bf32c 100644
--- a/Documentation/arm64/booting.rst
+++ b/Documentation/arm64/booting.rst
@@ -287,6 +287,24 @@ Before jumping into the kernel, the following conditions must be met:
- CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
+ For CPUs with the Scalable Vector Extension (FEAT_SVE) present:
+ - if EL3 is present:
+ - CPTR_EL3.EZ (bit 8) must be initialised to 0b1.
+ - ZCR_EL3.LEN must be initialised to the same value for all CPUs the
+ kernel is executed on.
+ - If the kernel is entered at EL1 and EL2 is present:
+ - CPTR_EL2.TZ (bit 8) must be initialised to 0b0.
+ - CPTR_EL2.ZEN (bits 17:16) must be initialised to 0b11.
+ - ZCR_EL2.LEN must be initialised to the same value for all CPUs the
+ kernel will execute on.
The requirements described above for CPU mode, caches, MMUs, architected
timers, coherency and system registers apply to all CPUs. All CPUs must
enter the kernel in the same exception level. Where the values documented