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authorChristoph Hellwig <hch@lst.de>2022-01-03 19:35:51 +0100
committerAlexei Starovoitov <ast@kernel.org>2022-01-05 13:11:26 -0800
commit62e4683849b6516c71e91f36e4fc0393a5883cfb (patch)
treee3104d09164f97e171b0b3d44d7d7371f6ad908e /Documentation/bpf/instruction-set.rst
parentbpf, selftests: Add verifier test for mem_or_null register with offset. (diff)
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bpf, docs: Add a setion to explain the basic instruction encoding
The eBPF instruction set document does not currently document the basic instruction encoding. Add a section to do that. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Alexei Starovoitov <ast@kernel.org> Link: https://lore.kernel.org/bpf/20220103183556.41040-2-hch@lst.de
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diff --git a/Documentation/bpf/instruction-set.rst b/Documentation/bpf/instruction-set.rst
index 1af51143ff9f..80f42984b594 100644
--- a/Documentation/bpf/instruction-set.rst
+++ b/Documentation/bpf/instruction-set.rst
@@ -19,8 +19,22 @@ The eBPF calling convention is defined as:
R0 - R5 are scratch registers and eBPF programs needs to spill/fill them if
necessary across calls.
+Instruction encoding
+====================
+
+eBPF uses 64-bit instructions with the following encoding:
+
+ ============= ======= =============== ==================== ============
+ 32 bits (MSB) 16 bits 4 bits 4 bits 8 bits (LSB)
+ ============= ======= =============== ==================== ============
+ immediate offset source register destination register opcode
+ ============= ======= =============== ==================== ============
+
+Note that most instructions do not use all of the fields.
+Unused fields shall be cleared to zero.
+
Instruction classes
-===================
+-------------------
The three LSB bits of the 'opcode' field store the instruction class: