path: root/Documentation/devicetree/bindings/bus/qcom,ebi2.txt
diff options
authorMasanari Iida <standby24x7@gmail.com>2017-01-05 23:43:07 +0900
committerRob Herring <robh@kernel.org>2017-01-09 12:18:32 -0600
commit2956b338b729dcce90f9fa5e799df71908f09701 (patch)
tree61a773e725693200dceb1ff97a04300ce1442261 /Documentation/devicetree/bindings/bus/qcom,ebi2.txt
parentdt-bindings: qman: Remove pool channel node (diff)
bus:qcom : Fix typo in qcom,ebi2.txt
This patch fix 2 spelling typos found in qcom,ebi2.txt Signed-off-by: Masanari Iida <standby24x7@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/bus/qcom,ebi2.txt')
1 files changed, 3 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/bus/qcom,ebi2.txt b/Documentation/devicetree/bindings/bus/qcom,ebi2.txt
index 920681f552db..5a7d567f6833 100644
--- a/Documentation/devicetree/bindings/bus/qcom,ebi2.txt
+++ b/Documentation/devicetree/bindings/bus/qcom,ebi2.txt
@@ -51,7 +51,7 @@ Required properties:
- compatible: should be one of:
-- #address-cells: shoule be <2>: the first cell is the chipselect,
+- #address-cells: should be <2>: the first cell is the chipselect,
the second cell is the offset inside the memory range
- #size-cells: should be <1>
- ranges: should be set to:
@@ -64,7 +64,7 @@ Required properties:
- reg: two ranges of registers: EBI2 config and XMEM config areas
- reg-names: should be "ebi2", "xmem"
- clocks: two clocks, EBI_2X and EBI
-- clock-names: shoule be "ebi2x", "ebi2"
+- clock-names: should be "ebi2x", "ebi2"
Optional subnodes:
- Nodes inside the EBI2 will be considered device nodes.
@@ -100,7 +100,7 @@ Optional properties arrays for FAST chip selects:
assertion, with respect to the cycle where ADV (address valid) is asserted.
2 means 2 cycles between ADV and OE. Valid values 0, 1, 2 or 3.
- qcom,xmem-read-hold-cycles: the length in cycles of the first segment of a
- read transfer. For a single read trandfer this will be the time from CS
+ read transfer. For a single read transfer this will be the time from CS
assertion to OE assertion. Valid values 0 thru 15.