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| author |   Conor Dooley <conor.dooley@microchip.com> | 2022-10-10 23:17:05 +0100 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2022-10-11 12:39:14 -0700 |
| commit | abbb388d335f8c400d1baecb15d360fa0062de77 (patch) | |
| tree | 2c21b91c5b0502cfcfd79113d7283b9bfb4fdb4f /Documentation/devicetree/bindings | |
| parent | MAINTAINERS: update polarfire soc clock binding (diff) | |
| download | linux-dev-abbb388d335f8c400d1baecb15d360fa0062de77.tar.xz linux-dev-abbb388d335f8c400d1baecb15d360fa0062de77.zip | |
dt-bindings: riscv: update microchip.yaml's maintainership
Daire and I are the platform maintainers for Microchip's RISC-V
FPGAs. Update the maintainers in microchip.yaml to reflect this and
explicitly add the binding to the SoC's MAINTAINERS entry.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221010221704.2161221-3-conor@kernel.org/
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'Documentation/devicetree/bindings')
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/microchip.yaml | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index 1aa7336a9672..9faf8447332b 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Microchip PolarFire SoC-based boards device tree bindings maintainers: - - Cyril Jean <Cyril.Jean@microchip.com> - - Lewis Hanly <lewis.hanly@microchip.com> + - Conor Dooley <conor.dooley@microchip.com> + - Daire McNamara <daire.mcnamara@microchip.com> description: Microchip PolarFire SoC-based boards |