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authorChen-Yu Tsai <wens@csie.org>2020-01-03 07:45:33 +0100
committerMauro Carvalho Chehab <mchehab+huawei@kernel.org>2020-01-04 08:21:35 +0100
commit51e40a0dbe53cebe1f4b85bb47e250dc5a89b254 (patch)
tree4e7f22dbccf59b63904497f6fd34a3c7c0838625 /Documentation/devicetree
parentmedia: sun4i-csi: Deal with DRAM offset (diff)
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media: sun4i-csi: Add support for A10 CSI1 camera sensor interface
The A10/A20 Allwinner SoCs have two camera sensor interface blocks, named CSI0 and CSI1. The two have the same register layouts with slightly different features: - CSI0 has an image signal processor (ISP); CSI1 doesn't - CSI0 can support up to four separate channels under CCIR656; CSI1 can only support one - CSI0 can support up to 16-bit wide bus with YUV422; CSI1 can support up to 24-bit wide bus with YUV444 For now the driver doesn't support wide busses, nor CCIR656. So the only relevant difference is whether a clock needs to be taken and enabled for the ISP. Add structs to record the differences, tie them to the compatible strings, and deal with the ISP clock. Support for the new CSI1 hardware block is added as well. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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