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| author |   SeongJae Park <sj38.park@gmail.com> | 2019-11-22 00:41:23 +0100 |
|---|---|---|
| committer |   Jonathan Corbet <corbet@lwn.net> | 2019-11-22 10:00:46 -0700 |
| commit | a897b13d1b77c8bd532a239adfd48c286a1b39ab (patch) | |
| tree | beb3b2b75a667fe4f63be45915bffdd111305831 /Documentation/memory-barriers.txt | |
| parent | docs/memory-barriers.txt/kokr: Update I/O section to be clearer about CPU vs thread (diff) | |
| download | linux-dev-a897b13d1b77c8bd532a239adfd48c286a1b39ab.tar.xz linux-dev-a897b13d1b77c8bd532a239adfd48c286a1b39ab.zip | |
docs/memory-barriers.txt: Remove remaining references to mmiowb()
This commit removes references to sections erased by Commit 915530396c78
("Documentation: Kill all references to mmiowb()").
Signed-off-by: SeongJae Park <sj38.park@gmail.com>
Link: https://lore.kernel.org/r/20191121234125.28032-6-sj38.park@gmail.com
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Diffstat (limited to 'Documentation/memory-barriers.txt')
| -rw-r--r-- | Documentation/memory-barriers.txt | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index 1adbb8a371c7..ec3b5865c1be 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -63,7 +63,6 @@ CONTENTS - Compiler barrier. - CPU memory barriers. - - MMIO write barrier. (*) Implicit kernel memory barriers. @@ -75,7 +74,6 @@ CONTENTS (*) Inter-CPU acquiring barrier effects. - Acquires vs memory accesses. - - Acquires vs I/O accesses. (*) Where are memory barriers needed? @@ -492,10 +490,9 @@ And a couple of implicit varieties: happen before it completes. The use of ACQUIRE and RELEASE operations generally precludes the need - for other sorts of memory barrier (but note the exceptions mentioned in - the subsection "MMIO write barrier"). In addition, a RELEASE+ACQUIRE - pair is -not- guaranteed to act as a full memory barrier. However, after - an ACQUIRE on a given variable, all memory accesses preceding any prior + for other sorts of memory barrier. In addition, a RELEASE+ACQUIRE pair is + -not- guaranteed to act as a full memory barrier. However, after an + ACQUIRE on a given variable, all memory accesses preceding any prior RELEASE on that same variable are guaranteed to be visible. In other words, within a given variable's critical section, all accesses of all previous critical sections for that variable are guaranteed to have @@ -1512,8 +1509,6 @@ levels: (*) CPU memory barriers. - (*) MMIO write barrier. - COMPILER BARRIER ---------------- |