diff options
| author |   Bruno Thomsen <bth@kamstrup.dk> | 2014-10-09 16:48:14 +0200 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2014-10-14 12:41:03 -0400 |
| commit | b838b4aced99e0d31a272396d43d9ca21cb078cb (patch) | |
| tree | 6c9710aa4ca8c55ab3932972734b8028b9925648 /MAINTAINERS | |
| parent | Merge branch 'bcmgenet_systemport' (diff) | |
| download | linux-dev-b838b4aced99e0d31a272396d43d9ca21cb078cb.tar.xz linux-dev-b838b4aced99e0d31a272396d43d9ca21cb078cb.zip | |
phy/micrel: KSZ8031RNL RMII clock reconfiguration bug
Bug: Unable to send and receive Ethernet packets with Micrel PHY.
Affected devices:
KSZ8031RNL (commercial temp)
KSZ8031RNLI (industrial temp)
Description:
PHY device is correctly detected during probe.
PHY power-up default is 25MHz crystal clock input
and output 50MHz RMII clock to MAC.
Reconfiguration of PHY to input 50MHz RMII clock from MAC
causes PHY to become unresponsive if clock source is changed
after Operation Mode Strap Override (OMSO) register setup.
Cause:
Long lead times on parts where clock setup match circuit design
forces the usage of similar parts with wrong default setup.
Solution:
Swapped KSZ8031 register setup and added phy_write return code validation.
Tested with Freescale i.MX28 Fast Ethernet Controler (fec).
Signed-off-by: Bruno Thomsen <bth@kamstrup.dk>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions