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authorVineet Gupta <vgupta@synopsys.com>2013-05-19 14:06:44 +0530
committerVineet Gupta <vgupta@synopsys.com>2013-05-23 14:25:09 +0530
commit006dfb3c9c44192f06093d65b3a876fa5ad1319a (patch)
treed3ea1716d564a7390141f12b98c628cfe4b932eb /arch/arc/mm/cache_arc700.c
parentARC: Brown paper bag bug in macro for checking cache color (diff)
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ARC: Use enough bits for determining page's cache color
The current code uses 2 bits for determining page's dcache color, thus sorting pages into 4 bins, whereas the aliasing dcache really has 2 bins (8k page, 64k dcache - 4 way-set-assoc). This can cause extraneous flushes - e.g. color 0 and 2. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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