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authorVineet Gupta <vgupta@synopsys.com>2017-08-22 14:37:22 -0700
committerVineet Gupta <vgupta@synopsys.com>2017-09-01 11:26:26 -0700
commit0fa400cb8a90753044bbcb5810fa1a59d96d5ea1 (patch)
tree76080e940d4b0fdde189ea918e80295a10f6e8c5 /arch/arc/mm/init.c
parentARC: [plat-axs103] use clk driver #2: Add core pll node to DT to manage cpu clk (diff)
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ARC: [plat-axs103] refactor the DT fudging code
with clk frequency setting code gone by prev commits, we can elide the unconditonal DT parsing to the specific case of quad core config where we possibly need to fudge the DT value. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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