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authorEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>2017-08-14 19:12:11 +0300
committerVineet Gupta <vgupta@synopsys.com>2017-09-01 11:26:25 -0700
commitf6a09bace0bb9587985b48ed652f2b292f8de0de (patch)
tree2d6a466f2c83b0ced16455c8291052103309d881 /arch/arc/plat-axs10x/axs10x.c
parentARC: [plat-axs103] use clk driver #1: Get rid of platform specific cpu clk setting (diff)
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ARC: [plat-axs103] use clk driver #2: Add core pll node to DT to manage cpu clk
Add core pll node (core_clk) to manage cpu frequency. core_clk represents pll itself. input_clk represents clock signal source (basically xtal) which comes to pll input. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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