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author | Sabrina Dubroca <sd@queasysnail.net> | 2017-07-03 13:02:55 +0200 |
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committer | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2017-10-09 07:43:06 -0700 |
commit | a39221ce969b316d3c3dcf7fcff8c0d8cf223007 (patch) | |
tree | 46aca632691ce385e45e57fcd0cd6391e0ab0f1d /arch/arc/plat-axs10x | |
parent | ixgbe: Return error when getting PHY address if PHY access is not supported (diff) | |
download | linux-dev-a39221ce969b316d3c3dcf7fcff8c0d8cf223007.tar.xz linux-dev-a39221ce969b316d3c3dcf7fcff8c0d8cf223007.zip |
ixgbe: fix masking of bits read from IXGBE_VXLANCTRL register
In ixgbe_clear_udp_tunnel_port(), we read the IXGBE_VXLANCTRL register
and then try to mask some bits out of the value, using the logical
instead of bitwise and operator.
Fixes: a21d0822ff69 ("ixgbe: add support for geneve Rx offload")
Signed-off-by: Sabrina Dubroca <sd@queasysnail.net>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'arch/arc/plat-axs10x')
0 files changed, 0 insertions, 0 deletions