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authorNoam Camus <noamc@ezchip.com>2012-08-19 11:54:33 +0300
committerVineet Gupta <vgupta@synopsys.com>2016-05-09 09:32:32 +0530
commit4a66d3fecf6554c4e1482774833da4f07cade787 (patch)
tree7d694c613677382bef4d822371ff44c805072753 /arch/arc/plat-eznps/Kconfig
parentARC: [plat-eznps] Add eznps board defconfig and dts (diff)
downloadlinux-dev-4a66d3fecf6554c4e1482774833da4f07cade787.tar.xz
linux-dev-4a66d3fecf6554c4e1482774833da4f07cade787.zip
ARC: [plat-eznps] Add eznps platform
This platform include boards: Hardware Emulator (HE) Simulator based upon nSIM. Signed-off-by: Noam Camus <noamc@ezchip.com>
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diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
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+#
+# For a description of the syntax of this configuration file,
+# see Documentation/kbuild/kconfig-language.txt.
+#
+
+menuconfig ARC_PLAT_EZNPS
+ bool "\"EZchip\" ARC dev platform"
+ select ARC_HAS_COH_CACHES if SMP
+ select CPU_BIG_ENDIAN
+ select CLKSRC_NPS
+ select EZNPS_GIC
+ select EZCHIP_NPS_MANAGEMENT_ENET if ETHERNET
+ help
+ Support for EZchip development platforms,
+ based on ARC700 cores.
+ We handle few flavours:
+ - Hardware Emulator AKA HE which is FPGA based chasis
+ - Simulator based on MetaWare nSIM
+ - NPS400 chip based on ASIC
+
+config EZNPS_MTM_EXT
+ bool "ARC-EZchip MTM Extensions"
+ select CPUMASK_OFFSTACK
+ depends on ARC_PLAT_EZNPS && SMP
+ default y
+ help
+ Here we add new hierarchy for CPUs topology.
+ We got:
+ Core
+ Thread
+ At the new thread level each CPU represent one HW thread.
+ At highest hierarchy each core contain 16 threads,
+ any of them seem like CPU from Linux point of view.
+ All threads within same core share the execution unit of the
+ core and HW scheduler round robin between them.