path: root/arch/arc/plat-eznps/mtm.c
diff options
authorElad Kanfi <eladkan@mellanox.com>2017-06-15 11:44:01 +0300
committerVineet Gupta <vgupta@synopsys.com>2017-08-28 15:17:36 -0700
commit3f9cd874dcc8705b53c03431f0ae46c94e572349 (patch)
treeb5a20f147f53b46dc3fd9e6f39f10686dceac152 /arch/arc/plat-eznps/mtm.c
parentARC: [plat-eznps] Update the init sequence of aux regs per cpu. (diff)
ARC: [plat-eznps] avoid toggling of DPC register
HW bug description: in case of HW thread context switch the dpc configuration of the exiting thread is dragged one cycle into the next thread. In order to avoid the consequences of this bug, the DPC register is set to an initial value, and not changed afterwards. Signed-off-by: Elad Kanfi <eladkan@mellanox.com> Signed-off-by: Noam Camus <noamca@mellanox.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to '')
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arc/plat-eznps/mtm.c b/arch/arc/plat-eznps/mtm.c
index 8a13f0ac49fb..2388de3d09ef 100644
--- a/arch/arc/plat-eznps/mtm.c
+++ b/arch/arc/plat-eznps/mtm.c
@@ -110,6 +110,18 @@ void mtm_enable_core(unsigned int cpu)
int i;
struct nps_host_reg_aux_mt_ctrl mt_ctrl;
struct nps_host_reg_mtm_cfg mtm_cfg;
+ struct nps_host_reg_aux_dpc dpc;
+ /*
+ * Initializing dpc register in each CPU.
+ * Overwriting the init value of the DPC
+ * register so that CMEM and FMT virtual address
+ * spaces are accessible, and Data Plane HW
+ * facilities are enabled.
+ */
+ dpc.ien = 1;
+ dpc.men = 1;
+ write_aux_reg(CTOP_AUX_DPC, dpc.value);
if (NPS_CPU_TO_THREAD_NUM(cpu) != 0)