path: root/arch/arc/plat-eznps/mtm.c
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authorLiav Rehana <liavr@mellanox.com>2017-06-15 11:43:58 +0300
committerVineet Gupta <vgupta@synopsys.com>2017-08-28 15:17:36 -0700
commitabd8926bff32df82d0fb8322b9fe382774f630b5 (patch)
treedded2b68ea705876809790fc14ab18720e103388 /arch/arc/plat-eznps/mtm.c
parentARC: [plat-eznps] new command line argument for HW scheduler at MTM (diff)
ARC: [plat-eznps] Update the init sequence of aux regs per cpu.
This commit add new configuration that enables us to distinguish between building the kernel for platforms that have a different set of auxiliary registers for each cpu and platforms that have a shared set of auxiliary registers across every thread in each core. On platforms that implement a different set of auxiliary registers disabling this configuration insures that we initialize registers on every cpu and not just for the first thread of the core. Example for non shared registers is working with EZsim (non silicon) Signed-off-by: Liav Rehana <liavr@mellanox.com> Signed-off-by: Noam Camus <noamca@mellanox.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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