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authorLiav Rehana <liavr@mellanox.com>2017-06-15 11:43:58 +0300
committerVineet Gupta <vgupta@synopsys.com>2017-08-28 15:17:36 -0700
commitabd8926bff32df82d0fb8322b9fe382774f630b5 (patch)
treedded2b68ea705876809790fc14ab18720e103388 /arch/arc
parentARC: [plat-eznps] new command line argument for HW scheduler at MTM (diff)
downloadlinux-dev-abd8926bff32df82d0fb8322b9fe382774f630b5.tar.xz
linux-dev-abd8926bff32df82d0fb8322b9fe382774f630b5.zip
ARC: [plat-eznps] Update the init sequence of aux regs per cpu.
This commit add new configuration that enables us to distinguish between building the kernel for platforms that have a different set of auxiliary registers for each cpu and platforms that have a shared set of auxiliary registers across every thread in each core. On platforms that implement a different set of auxiliary registers disabling this configuration insures that we initialize registers on every cpu and not just for the first thread of the core. Example for non shared registers is working with EZsim (non silicon) Signed-off-by: Liav Rehana <liavr@mellanox.com> Signed-off-by: Noam Camus <noamca@mellanox.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to '')
-rw-r--r--arch/arc/plat-eznps/Kconfig11
-rw-r--r--arch/arc/plat-eznps/entry.S2
2 files changed, 12 insertions, 1 deletions
diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
index b36afb1feaba..e151e2067886 100644
--- a/arch/arc/plat-eznps/Kconfig
+++ b/arch/arc/plat-eznps/Kconfig
@@ -43,3 +43,14 @@ config EZNPS_MEM_ERROR_ALIGN
simulator platform for NPS, is handled as a Level 2 interrupt
(just a stock ARC700) which is recoverable. This option makes
simulator behave like hardware.
+
+config EZNPS_SHARED_AUX_REGS
+ bool "ARC-EZchip Shared Auxiliary Registers Per Core"
+ depends on ARC_PLAT_EZNPS
+ default y
+ help
+ On the real chip of the NPS, auxiliary registers are shared between
+ all the cpus of the core, whereas on simulator platform for NPS,
+ each cpu has a different set of auxiliary registers. Configuration
+ should be unset if auxiliary registers are not shared between the cpus
+ of the core, so there will be a need to initialize them per cpu.
diff --git a/arch/arc/plat-eznps/entry.S b/arch/arc/plat-eznps/entry.S
index 328261c27cda..091c92c32ab6 100644
--- a/arch/arc/plat-eznps/entry.S
+++ b/arch/arc/plat-eznps/entry.S
@@ -27,7 +27,7 @@
.align 1024 ; HW requierment for restart first PC
ENTRY(res_service)
-#ifdef CONFIG_EZNPS_MTM_EXT
+#if defined(CONFIG_EZNPS_MTM_EXT) && defined(CONFIG_EZNPS_SHARED_AUX_REGS)
; There is no work for HW thread id != 0
lr r3, [CTOP_AUX_THREAD_ID]
cmp r3, 0