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authorLinus Torvalds <torvalds@linux-foundation.org>2020-02-08 13:58:44 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2020-02-08 13:58:44 -0800
commit1afa9c3b7c9bdcb562e2afe9f58cc99d0b071cdc (patch)
tree666fa74b364da962fbd8297c477fbe368874b5be /arch/arm/boot/dts
parentMerge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc (diff)
parentMerge tag 'ti-k3-soc-for-v5.6-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into arm/dt (diff)
downloadlinux-dev-1afa9c3b7c9bdcb562e2afe9f58cc99d0b071cdc.tar.xz
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM Device-tree updates from Olof Johansson: "New SoCs: - Atmel/Microchip SAM9X60 (ARM926 SoC) - OMAP 37xx gets split into AM3703/AM3715/DM3725, who are all variants of it with different GPU/media IP configurations. - ST stm32mp15 SoCs (1-2 Cortex-A7, CAN, GPU depending on SKU) - ST Ericsson ab8505 (variant of ab8500) and db8520 (variant of db8500) - Unisoc SC9863A SoC (8x Cortex-A55 mobile chipset w/ GPU, modem) - Qualcomm SC7180 (8-core 64bit SoC, unnamed CPU class) New boards: - Allwinner: + Emlid Neutis SoM (H3 variant) + Libre Computer ALL-H3-IT + PineH64 Model B - Amlogic: + Libretech Amlogic GX PC (s905d and s912-based variants) - Atmel/Microchip: + Kizboxmini, sam9x60 EK, sama5d27 Wireless SOM (wlsom1) - Marvell: + Armada 385-based SolidRun Clearfog GTR - NXP: + Gateworks GW59xx boards based on i.MX6/6Q/6QDL + Tolino Shine 3 eBook reader (i.MX6sl) + Embedded Artists COM (i.MX7ULP) + SolidRun CLearfog CX/ITX and HoneyComb (LX2160A-based systems) + Google Coral Edge TPU (i.MX8MQ) - Rockchip: + Radxa Dalang Carrier (supports rk3288 and rk3399 SOMs) + Radxa Rock Pi N10 (RK3399Pro-based) + VMARC RK3399Pro SOM - ST: + Reference boards for stm32mp15 - ST Ericsson: + Samsung Galaxy S III mini (GT-I8190) + HREF520 reference board for DB8520 - TI OMAP: + Gen1 Amazon Echo (OMAP3630-based) - Qualcomm: + Inforce 6640 Single Board Computer (msm8996-based) + SC7180 IDP (SC7180-based)" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (623 commits) dt-bindings: fix compilation error of the example in marvell,mmp3-hsic-phy.yaml arm64: dts: ti: k3-am654-base-board: Add CSI2 OV5640 camera arm64: dts: ti: k3-am65-main Add CAL node arm64: dts: ti: k3-j721e-main: Add McASP nodes arm64: dts: ti: k3-am654-main: Add McASP nodes arm64: dts: ti: k3-j721e: DMA support arm64: dts: ti: k3-j721e-main: Move secure proxy and smmu under main_navss arm64: dts: ti: k3-j721e-main: Correct main NAVSS representation arm64: dts: ti: k3-j721e: Correct the address for MAIN NAVSS arm64: dts: ti: k3-am65: DMA support arm64: dts: ti: k3-am65-main: Move secure proxy under cbass_main_navss arm64: dts: ti: k3-am65-main: Correct main NAVSS representation ARM: dts: aspeed: rainier: Add UCD90320 power sequencer ARM: dts: aspeed: rainier: Switch PSUs to unknown version arm64: dts: rockchip: Kill off "simple-panel" compatibles ARM: dts: rockchip: Kill off "simple-panel" compatibles arm64: dts: rockchip: rename dwmmc node names to mmc ARM: dts: rockchip: rename dwmmc node names to mmc arm64: dts: exynos: Rename Samsung and Exynos to lowercase arm64: dts: uniphier: add reset-names to NAND controller node ...
Diffstat (limited to 'arch/arm/boot/dts')
-rw-r--r--arch/arm/boot/dts/Makefile26
-rw-r--r--arch/arm/boot/dts/am335x-evm.dts40
-rw-r--r--arch/arm/boot/dts/am335x-evmsk.dts38
-rw-r--r--arch/arm/boot/dts/am335x-icev2.dts13
-rw-r--r--arch/arm/boot/dts/am33xx-l4.dtsi16
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi69
-rw-r--r--arch/arm/boot/dts/am3517.dtsi2
-rw-r--r--arch/arm/boot/dts/am3703.dtsi14
-rw-r--r--arch/arm/boot/dts/am3715.dtsi10
-rw-r--r--arch/arm/boot/dts/am4372.dtsi142
-rw-r--r--arch/arm/boot/dts/am437x-l4.dtsi29
-rw-r--r--arch/arm/boot/dts/am57xx-idk-common.dtsi59
-rw-r--r--arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts115
-rw-r--r--arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts79
-rw-r--r--arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi450
-rw-r--r--arch/arm/boot/dts/armada-388-clearfog.dtsi11
-rw-r--r--arch/arm/boot/dts/armada-388-helios4.dts5
-rw-r--r--arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi13
-rw-r--r--arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts1
-rw-r--r--arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts1
-rw-r--r--arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts1
-rw-r--r--arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts20
-rw-r--r--arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts2
-rw-r--r--arch/arm/boot/dts/aspeed-bmc-opp-swift.dts2
-rw-r--r--arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts18
-rw-r--r--arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts2
-rw-r--r--arch/arm/boot/dts/aspeed-g4.dtsi21
-rw-r--r--arch/arm/boot/dts/aspeed-g5.dtsi49
-rw-r--r--arch/arm/boot/dts/aspeed-g6.dtsi2
-rw-r--r--arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi1
-rw-r--r--arch/arm/boot/dts/at91-kizbox.dts172
-rw-r--r--arch/arm/boot/dts/at91-kizboxmini-base.dts24
-rw-r--r--arch/arm/boot/dts/at91-kizboxmini-common.dtsi (renamed from arch/arm/boot/dts/at91-kizboxmini.dts)163
-rw-r--r--arch/arm/boot/dts/at91-kizboxmini-mb.dts26
-rw-r--r--arch/arm/boot/dts/at91-kizboxmini-rd.dts49
-rw-r--r--arch/arm/boot/dts/at91-nattis-2-natte-2.dts1
-rw-r--r--arch/arm/boot/dts/at91-sam9x60ek.dts647
-rw-r--r--arch/arm/boot/dts/at91-sama5d27_som1.dtsi4
-rw-r--r--arch/arm/boot/dts/at91-sama5d27_som1_ek.dts6
-rw-r--r--arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi304
-rw-r--r--arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts270
-rw-r--r--arch/arm/boot/dts/at91-smartkiz.dts109
-rw-r--r--arch/arm/boot/dts/at91sam9260.dtsi16
-rw-r--r--arch/arm/boot/dts/at91sam9261.dtsi6
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi6
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi8
-rw-r--r--arch/arm/boot/dts/at91sam9rl.dtsi8
-rw-r--r--arch/arm/boot/dts/bcm2711.dtsi70
-rw-r--r--arch/arm/boot/dts/bcm2835-common.dtsi6
-rw-r--r--arch/arm/boot/dts/bcm283x.dtsi19
-rw-r--r--arch/arm/boot/dts/bcm958625hr.dts15
-rw-r--r--arch/arm/boot/dts/dm3725.dtsi10
-rw-r--r--arch/arm/boot/dts/dra7-l4.dtsi55
-rw-r--r--arch/arm/boot/dts/dra7.dtsi258
-rw-r--r--arch/arm/boot/dts/dra74x.dtsi71
-rw-r--r--arch/arm/boot/dts/dra76-evm.dts66
-rw-r--r--arch/arm/boot/dts/e60k02.dtsi3
-rw-r--r--arch/arm/boot/dts/exynos3250.dtsi4
-rw-r--r--arch/arm/boot/dts/exynos4210-universal_c210.dts6
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi4
-rw-r--r--arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi5
-rw-r--r--arch/arm/boot/dts/exynos4412-midas.dtsi29
-rw-r--r--arch/arm/boot/dts/exynos4412-n710x.dts5
-rw-r--r--arch/arm/boot/dts/exynos4412-odroid-common.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos4412-tiny4412.dts25
-rw-r--r--arch/arm/boot/dts/exynos4412.dtsi4
-rw-r--r--arch/arm/boot/dts/exynos5.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos5250-arndale.dts4
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts4
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi12
-rw-r--r--arch/arm/boot/dts/exynos5260-xyref5260.dts4
-rw-r--r--arch/arm/boot/dts/exynos5260.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos5410-odroidxu.dts2
-rw-r--r--arch/arm/boot/dts/exynos5410-smdk5410.dts4
-rw-r--r--arch/arm/boot/dts/exynos5410.dtsi6
-rw-r--r--arch/arm/boot/dts/exynos5420-arndale-octa.dts2
-rw-r--r--arch/arm/boot/dts/exynos5420-cpus.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos5420-smdk5420.dts4
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi339
-rw-r--r--arch/arm/boot/dts/exynos5422-cpus.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos5422-odroid-core.dtsi285
-rw-r--r--arch/arm/boot/dts/exynos5422-odroidhc1.dts64
-rw-r--r--arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi78
-rw-r--r--arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts58
-rw-r--r--arch/arm/boot/dts/exynos54xx.dtsi4
-rw-r--r--arch/arm/boot/dts/exynos5800-peach-pi.dts13
-rw-r--r--arch/arm/boot/dts/exynos5800.dtsi58
-rw-r--r--arch/arm/boot/dts/ibm-power9-dual.dtsi4
-rw-r--r--arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts2
-rw-r--r--arch/arm/boot/dts/imx25-pdk.dts2
-rw-r--r--arch/arm/boot/dts/imx25.dtsi3
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts64
-rw-r--r--arch/arm/boot/dts/imx6dl-gw5907.dts14
-rw-r--r--arch/arm/boot/dts/imx6dl-gw5910.dts14
-rw-r--r--arch/arm/boot/dts/imx6dl-gw5912.dts13
-rw-r--r--arch/arm/boot/dts/imx6dl-gw5913.dts14
-rw-r--r--arch/arm/boot/dts/imx6q-gw5907.dts14
-rw-r--r--arch/arm/boot/dts/imx6q-gw5910.dts14
-rw-r--r--arch/arm/boot/dts/imx6q-gw5912.dts13
-rw-r--r--arch/arm/boot/dts/imx6q-gw5913.dts14
-rw-r--r--arch/arm/boot/dts/imx6q-logicpd.dts10
-rw-r--r--arch/arm/boot/dts/imx6qdl-apalis.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw5907.dtsi399
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw5910.dtsi491
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw5912.dtsi461
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw5913.dtsi348
-rw-r--r--arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6qdl-icore.dtsi15
-rw-r--r--arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi9
-rw-r--r--arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi84
-rw-r--r--arch/arm/boot/dts/imx6sl-tolino-shine3.dts322
-rw-r--r--arch/arm/boot/dts/imx6sll.dtsi9
-rw-r--r--arch/arm/boot/dts/imx6sx-sdb-reva.dts1
-rw-r--r--arch/arm/boot/dts/imx6ul-14x14-evk.dtsi1
-rw-r--r--arch/arm/boot/dts/imx6ull-colibri.dtsi188
-rw-r--r--arch/arm/boot/dts/imx7d-pico.dtsi90
-rw-r--r--arch/arm/boot/dts/imx7d-sdb-reva.dts3
-rw-r--r--arch/arm/boot/dts/imx7d.dtsi2
-rw-r--r--arch/arm/boot/dts/imx7s.dtsi16
-rw-r--r--arch/arm/boot/dts/imx7ulp-com.dts79
-rw-r--r--arch/arm/boot/dts/iwg20d-q7-common.dtsi88
-rw-r--r--arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi1
-rw-r--r--arch/arm/boot/dts/ls1021a-tsn.dts4
-rw-r--r--arch/arm/boot/dts/ls1021a.dtsi19
-rw-r--r--arch/arm/boot/dts/meson.dtsi7
-rw-r--r--arch/arm/boot/dts/meson6.dtsi7
-rw-r--r--arch/arm/boot/dts/meson8.dtsi28
-rw-r--r--arch/arm/boot/dts/meson8b-ec100.dts2
-rw-r--r--arch/arm/boot/dts/meson8b-mxq.dts2
-rw-r--r--arch/arm/boot/dts/meson8b-odroidc1.dts2
-rw-r--r--arch/arm/boot/dts/meson8b.dtsi30
-rw-r--r--arch/arm/boot/dts/mmp3-dell-ariel.dts22
-rw-r--r--arch/arm/boot/dts/mmp3.dtsi44
-rw-r--r--arch/arm/boot/dts/omap2.dtsi43
-rw-r--r--arch/arm/boot/dts/omap2430.dtsi4
-rw-r--r--arch/arm/boot/dts/omap3-echo.dts461
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts5
-rw-r--r--arch/arm/boot/dts/omap3.dtsi46
-rw-r--r--arch/arm/boot/dts/omap36xx.dtsi4
-rw-r--r--arch/arm/boot/dts/omap4-l4-abe.dtsi7
-rw-r--r--arch/arm/boot/dts/omap4-l4.dtsi30
-rw-r--r--arch/arm/boot/dts/omap4.dtsi44
-rw-r--r--arch/arm/boot/dts/omap5-l4-abe.dtsi6
-rw-r--r--arch/arm/boot/dts/omap5-l4.dtsi24
-rw-r--r--arch/arm/boot/dts/omap5.dtsi40
-rw-r--r--arch/arm/boot/dts/qcom-apq8084.dtsi44
-rw-r--r--arch/arm/boot/dts/qcom-ipq4019.dtsi7
-rw-r--r--arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts45
-rw-r--r--arch/arm/boot/dts/qcom-msm8974.dtsi222
-rw-r--r--arch/arm/boot/dts/r7s72100.dtsi18
-rw-r--r--arch/arm/boot/dts/r8a73a4.dtsi42
-rw-r--r--arch/arm/boot/dts/r8a7740-armadillo800eva.dts3
-rw-r--r--arch/arm/boot/dts/r8a7740.dtsi102
-rw-r--r--arch/arm/boot/dts/r8a7743.dtsi162
-rw-r--r--arch/arm/boot/dts/r8a7744.dtsi162
-rw-r--r--arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts3
-rw-r--r--arch/arm/boot/dts/r8a7745.dtsi122
-rw-r--r--arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts3
-rw-r--r--arch/arm/boot/dts/r8a77470.dtsi86
-rw-r--r--arch/arm/boot/dts/r8a7778.dtsi11
-rw-r--r--arch/arm/boot/dts/r8a7779-marzen.dts3
-rw-r--r--arch/arm/boot/dts/r8a7779.dtsi16
-rw-r--r--arch/arm/boot/dts/r8a7790-lager.dts6
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi167
-rw-r--r--arch/arm/boot/dts/r8a7791-koelsch.dts9
-rw-r--r--arch/arm/boot/dts/r8a7791-porter.dts6
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi159
-rw-r--r--arch/arm/boot/dts/r8a7792.dtsi67
-rw-r--r--arch/arm/boot/dts/r8a7793-gose.dts9
-rw-r--r--arch/arm/boot/dts/r8a7793.dtsi123
-rw-r--r--arch/arm/boot/dts/r8a7794-alt.dts6
-rw-r--r--arch/arm/boot/dts/r8a7794-silk.dts3
-rw-r--r--arch/arm/boot/dts/r8a7794.dtsi111
-rw-r--r--arch/arm/boot/dts/rk3036.dtsi6
-rw-r--r--arch/arm/boot/dts/rk3188-bqedison2qc.dts3
-rw-r--r--arch/arm/boot/dts/rk322x.dtsi6
-rw-r--r--arch/arm/boot/dts/rk3288-evb.dtsi2
-rw-r--r--arch/arm/boot/dts/rk3288-tinker.dtsi13
-rw-r--r--arch/arm/boot/dts/rk3288-veyron-brain.dts9
-rw-r--r--arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi22
-rw-r--r--arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi21
-rw-r--r--arch/arm/boot/dts/rk3288-veyron-edp.dtsi2
-rw-r--r--arch/arm/boot/dts/rk3288-veyron-fievel.dts14
-rw-r--r--arch/arm/boot/dts/rk3288-veyron-jaq.dts22
-rw-r--r--arch/arm/boot/dts/rk3288-veyron-jerry.dts22
-rw-r--r--arch/arm/boot/dts/rk3288-veyron-mickey.dts9
-rw-r--r--arch/arm/boot/dts/rk3288-veyron-minnie.dts23
-rw-r--r--arch/arm/boot/dts/rk3288-veyron-pinky.dts22
-rw-r--r--arch/arm/boot/dts/rk3288-veyron-speedy.dts21
-rw-r--r--arch/arm/boot/dts/rk3288-veyron-tiger.dts2
-rw-r--r--arch/arm/boot/dts/rk3288-veyron.dtsi59
-rw-r--r--arch/arm/boot/dts/rk3288.dtsi8
-rw-r--r--arch/arm/boot/dts/rk3xxx.dtsi6
-rw-r--r--arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi81
-rw-r--r--arch/arm/boot/dts/rv1108.dtsi6
-rw-r--r--arch/arm/boot/dts/s3c2416-smdk2416.dts2
-rw-r--r--arch/arm/boot/dts/s3c6410-smdk6410.dts4
-rw-r--r--arch/arm/boot/dts/sam9x60.dtsi691
-rw-r--r--arch/arm/boot/dts/sama5d2.dtsi10
-rw-r--r--arch/arm/boot/dts/sama5d3.dtsi28
-rw-r--r--arch/arm/boot/dts/sama5d3_can.dtsi4
-rw-r--r--arch/arm/boot/dts/sama5d3_tcb1.dtsi1
-rw-r--r--arch/arm/boot/dts/sama5d3_uart.dtsi4
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi139
-rw-r--r--arch/arm/boot/dts/ste-ab8500.dtsi102
-rw-r--r--arch/arm/boot/dts/ste-ab8505.dtsi275
-rw-r--r--arch/arm/boot/dts/ste-db8500.dtsi15
-rw-r--r--arch/arm/boot/dts/ste-db8520.dtsi15
-rw-r--r--arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi632
-rw-r--r--arch/arm/boot/dts/ste-dbx5x0.dtsi75
-rw-r--r--arch/arm/boot/dts/ste-href-ab8505.dtsi234
-rw-r--r--arch/arm/boot/dts/ste-href-family-pinctrl.dtsi532
-rw-r--r--arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi79
-rw-r--r--arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi58
-rw-r--r--arch/arm/boot/dts/ste-href-tvk1281618.dtsi71
-rw-r--r--arch/arm/boot/dts/ste-href.dtsi67
-rw-r--r--arch/arm/boot/dts/ste-href520-tvk.dts22
-rw-r--r--arch/arm/boot/dts/ste-hrefprev60-stuib.dts10
-rw-r--r--arch/arm/boot/dts/ste-hrefprev60-tvk.dts10
-rw-r--r--arch/arm/boot/dts/ste-hrefprev60.dtsi2
-rw-r--r--arch/arm/boot/dts/ste-hrefv60plus-stuib.dts10
-rw-r--r--arch/arm/boot/dts/ste-hrefv60plus-tvk.dts10
-rw-r--r--arch/arm/boot/dts/ste-hrefv60plus.dtsi1
-rw-r--r--arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi5
-rw-r--r--arch/arm/boot/dts/ste-snowball.dts70
-rw-r--r--arch/arm/boot/dts/ste-ux500-samsung-golden.dts455
-rw-r--r--arch/arm/boot/dts/stm32429i-eval.dts8
-rw-r--r--arch/arm/boot/dts/stm32f4-pinctrl.dtsi28
-rw-r--r--arch/arm/boot/dts/stm32f429.dtsi4
-rw-r--r--arch/arm/boot/dts/stm32f469-disco.dts8
-rw-r--r--arch/arm/boot/dts/stm32f7-pinctrl.dtsi22
-rw-r--r--arch/arm/boot/dts/stm32f746.dtsi5
-rw-r--r--arch/arm/boot/dts/stm32h743.dtsi6
-rw-r--r--arch/arm/boot/dts/stm32mp15-pinctrl.dtsi1092
-rw-r--r--arch/arm/boot/dts/stm32mp151.dtsi (renamed from arch/arm/boot/dts/stm32mp157c.dtsi)301
-rw-r--r--arch/arm/boot/dts/stm32mp153.dtsi45
-rw-r--r--arch/arm/boot/dts/stm32mp157-pinctrl.dtsi953
-rw-r--r--arch/arm/boot/dts/stm32mp157.dtsi31
-rw-r--r--arch/arm/boot/dts/stm32mp157a-avenger96.dts5
-rw-r--r--arch/arm/boot/dts/stm32mp157a-dk1.dts498
-rw-r--r--arch/arm/boot/dts/stm32mp157c-dk2.dts15
-rw-r--r--arch/arm/boot/dts/stm32mp157c-ed1.dts38
-rw-r--r--arch/arm/boot/dts/stm32mp157c-ev1.dts22
-rw-r--r--arch/arm/boot/dts/stm32mp157xaa-pinctrl.dtsi90
-rw-r--r--arch/arm/boot/dts/stm32mp157xab-pinctrl.dtsi62
-rw-r--r--arch/arm/boot/dts/stm32mp157xac-pinctrl.dtsi78
-rw-r--r--arch/arm/boot/dts/stm32mp157xad-pinctrl.dtsi62
-rw-r--r--arch/arm/boot/dts/stm32mp15xc.dtsi18
-rw-r--r--arch/arm/boot/dts/stm32mp15xx-dkx.dtsi625
-rw-r--r--arch/arm/boot/dts/stm32mp15xxaa-pinctrl.dtsi85
-rw-r--r--arch/arm/boot/dts/stm32mp15xxab-pinctrl.dtsi57
-rw-r--r--arch/arm/boot/dts/stm32mp15xxac-pinctrl.dtsi73
-rw-r--r--arch/arm/boot/dts/stm32mp15xxad-pinctrl.dtsi57
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi35
-rw-r--r--arch/arm/boot/dts/sun5i.dtsi3
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi25
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi36
-rw-r--r--arch/arm/boot/dts/sun8i-a23-a33.dtsi13
-rw-r--r--arch/arm/boot/dts/sun8i-a83t.dtsi42
-rw-r--r--arch/arm/boot/dts/sun8i-h3-beelink-x2.dts1
-rw-r--r--arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3-devboard.dts72
-rw-r--r--arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi11
-rw-r--r--arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts3
-rw-r--r--arch/arm/boot/dts/sun8i-h3.dtsi35
-rw-r--r--arch/arm/boot/dts/sun8i-r40.dtsi172
-rw-r--r--arch/arm/boot/dts/sun8i-v3s.dtsi2
-rw-r--r--arch/arm/boot/dts/sun9i-a80.dtsi42
-rw-r--r--arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi170
-rw-r--r--arch/arm/boot/dts/sunxi-h3-h5.dtsi13
-rw-r--r--arch/arm/boot/dts/sunxi-libretech-all-h3-it.dtsi180
-rw-r--r--arch/arm/boot/dts/tegra124-apalis-emc.dtsi2
-rw-r--r--arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi2
-rw-r--r--arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi2
-rw-r--r--arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi2
-rw-r--r--arch/arm/boot/dts/tegra124.dtsi4
-rw-r--r--arch/arm/boot/dts/tegra20-paz00.dts46
-rw-r--r--arch/arm/boot/dts/uniphier-ld4.dtsi3
-rw-r--r--arch/arm/boot/dts/uniphier-pinctrl.dtsi10
-rw-r--r--arch/arm/boot/dts/uniphier-pro4.dtsi3
-rw-r--r--arch/arm/boot/dts/uniphier-pro5.dtsi3
-rw-r--r--arch/arm/boot/dts/uniphier-pxs2.dtsi3
-rw-r--r--arch/arm/boot/dts/uniphier-sld8.dtsi3
-rw-r--r--arch/arm/boot/dts/vf610-zii-dev-rev-b.dts10
-rw-r--r--arch/arm/boot/dts/vf610-zii-scu4-aib.dts29
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi135
285 files changed, 14444 insertions, 5048 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 08011dc8c7a6..d6546d2676b9 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -37,18 +37,24 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
at91-ariag25.dtb \
at91-ariettag25.dtb \
at91-cosino_mega2560.dtb \
- at91-kizboxmini.dtb \
+ at91-kizboxmini-base.dtb \
+ at91-kizboxmini-mb.dtb \
+ at91-kizboxmini-rd.dtb \
+ at91-smartkiz.dtb \
at91-wb45n.dtb \
at91sam9g15ek.dtb \
at91sam9g25ek.dtb \
at91sam9g35ek.dtb \
at91sam9x25ek.dtb \
at91sam9x35ek.dtb
+dtb-$(CONFIG_SOC_SAM9X60) += \
+ at91-sam9x60ek.dtb
dtb-$(CONFIG_SOC_SAM_V7) += \
at91-kizbox2-2.dtb \
at91-kizbox3-hs.dtb \
at91-nattis-2-natte-2.dtb \
at91-sama5d27_som1_ek.dtb \
+ at91-sama5d27_wlsom1_ek.dtb \
at91-sama5d2_ptc_ek.dtb \
at91-sama5d2_xplained.dtb \
at91-sama5d3_xplained.dtb \
@@ -422,6 +428,10 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-gw560x.dtb \
imx6dl-gw5903.dtb \
imx6dl-gw5904.dtb \
+ imx6dl-gw5907.dtb \
+ imx6dl-gw5910.dtb \
+ imx6dl-gw5912.dtb \
+ imx6dl-gw5913.dtb \
imx6dl-hummingboard.dtb \
imx6dl-hummingboard-emmc-som-v15.dtb \
imx6dl-hummingboard-som-v15.dtb \
@@ -493,6 +503,10 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-gw560x.dtb \
imx6q-gw5903.dtb \
imx6q-gw5904.dtb \
+ imx6q-gw5907.dtb \
+ imx6q-gw5910.dtb \
+ imx6q-gw5912.dtb \
+ imx6q-gw5913.dtb \
imx6q-h100.dtb \
imx6q-hummingboard.dtb \
imx6q-hummingboard-emmc-som-v15.dtb \
@@ -554,6 +568,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6qp-zii-rdu2.dtb
dtb-$(CONFIG_SOC_IMX6SL) += \
imx6sl-evk.dtb \
+ imx6sl-tolino-shine3.dtb \
imx6sl-warp.dtb
dtb-$(CONFIG_SOC_IMX6SLL) += \
imx6sll-evk.dtb \
@@ -612,6 +627,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \
imx7s-mba7.dtb \
imx7s-warp.dtb
dtb-$(CONFIG_SOC_IMX7ULP) += \
+ imx7ulp-com.dtb \
imx7ulp-evk.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-moxa-uc-8410a.dtb \
@@ -691,6 +707,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += \
omap3-devkit8000.dtb \
omap3-devkit8000-lcd43.dtb \
omap3-devkit8000-lcd70.dtb \
+ omap3-echo.dtb \
omap3-evm.dtb \
omap3-evm-37xx.dtb \
omap3-gta04a3.dtb \
@@ -1129,6 +1146,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-h3-orangepi-plus2e.dtb \
sun8i-h3-orangepi-zero-plus2.dtb \
sun8i-h3-rervision-dvk.dtb \
+ sun8i-h3-emlid-neutis-n5h3-devboard.dtb \
sun8i-r16-bananapi-m2m.dtb \
sun8i-r16-nintendo-nes-classic.dtb \
sun8i-r16-nintendo-super-nes-classic.dtb \
@@ -1182,7 +1200,9 @@ dtb-$(CONFIG_ARCH_U8500) += \
ste-hrefprev60-stuib.dtb \
ste-hrefprev60-tvk.dtb \
ste-hrefv60plus-stuib.dtb \
- ste-hrefv60plus-tvk.dtb
+ ste-hrefv60plus-tvk.dtb \
+ ste-href520-tvk.dtb \
+ ste-ux500-samsung-golden.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ld4-ref.dtb \
uniphier-ld6b-ref.dtb \
@@ -1238,6 +1258,8 @@ dtb-$(CONFIG_MACH_ARMADA_370) += \
dtb-$(CONFIG_MACH_ARMADA_375) += \
armada-375-db.dtb
dtb-$(CONFIG_MACH_ARMADA_38X) += \
+ armada-385-clearfog-gtr-s4.dtb \
+ armada-385-clearfog-gtr-l8.dtb \
armada-385-db-88f6820-amc.dtb \
armada-385-db-ap.dtb \
armada-385-linksys-caiman.dtb \
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 6f0a6be93098..68252dab32c3 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -113,7 +113,7 @@
};
};
- backlight {
+ backlight: backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 0>;
brightness-levels = <0 51 53 56 62 75 101 152 255>;
@@ -121,35 +121,15 @@
};
panel {
- compatible = "ti,tilcdc,panel";
- status = "okay";
+ compatible = "tfc,s9700rtwv43tr-01b";
+
pinctrl-names = "default";
pinctrl-0 = <&lcd_pins_s0>;
- panel-info {
- ac-bias = <255>;
- ac-bias-intrpt = <0>;
- dma-burst-sz = <16>;
- bpp = <32>;
- fdd = <0x80>;
- sync-edge = <0>;
- sync-ctrl = <1>;
- raster-order = <0>;
- fifo-th = <0>;
- };
+ backlight = <&backlight>;
- display-timings {
- 800x480p62 {
- clock-frequency = <30000000>;
- hactive = <800>;
- vactive = <480>;
- hfront-porch = <39>;
- hback-porch = <39>;
- hsync-len = <47>;
- vback-porch = <29>;
- vfront-porch = <13>;
- vsync-len = <2>;
- hsync-active = <1>;
- vsync-active = <1>;
+ port {
+ panel_0: endpoint@0 {
+ remote-endpoint = <&lcdc_0>;
};
};
};
@@ -500,6 +480,12 @@
status = "okay";
blue-and-red-wiring = "crossed";
+
+ port {
+ lcdc_0: endpoint@0 {
+ remote-endpoint = <&panel_0>;
+ };
+ };
};
&elm {
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index a97f9df460c1..32f515a295ee 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -183,36 +183,16 @@
};
panel {
- compatible = "ti,tilcdc,panel";
+ compatible = "newhaven,nhd-4.3-480272ef-atxl";
+
pinctrl-names = "default", "sleep";
pinctrl-0 = <&lcd_pins_default>;
pinctrl-1 = <&lcd_pins_sleep>;
backlight = <&lcd_bl>;
- status = "okay";
- panel-info {
- ac-bias = <255>;
- ac-bias-intrpt = <0>;
- dma-burst-sz = <16>;
- bpp = <32>;
- fdd = <0x80>;
- sync-edge = <0>;
- sync-ctrl = <1>;
- raster-order = <0>;
- fifo-th = <0>;
- };
- display-timings {
- 480x272 {
- hactive = <480>;
- vactive = <272>;
- hback-porch = <43>;
- hfront-porch = <8>;
- hsync-len = <4>;
- vback-porch = <12>;
- vfront-porch = <4>;
- vsync-len = <10>;
- clock-frequency = <9000000>;
- hsync-active = <0>;
- vsync-active = <0>;
+
+ port {
+ panel_0: endpoint@0 {
+ remote-endpoint = <&lcdc_0>;
};
};
};
@@ -725,6 +705,12 @@
status = "okay";
blue-and-red-wiring = "crossed";
+
+ port {
+ lcdc_0: endpoint@0 {
+ remote-endpoint = <&panel_0>;
+ };
+ };
};
&rtc {
diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts
index 204bccfcc110..021eb57261fe 100644
--- a/arch/arm/boot/dts/am335x-icev2.dts
+++ b/arch/arm/boot/dts/am335x-icev2.dts
@@ -287,6 +287,19 @@
gpio-controller;
#gpio-cells = <2>;
};
+
+ /* osd9616p0899-10 */
+ display@3c {
+ compatible = "solomon,ssd1306fb-i2c";
+ reg = <0x3c>;
+ solomon,height = <16>;
+ solomon,width = <96>;
+ solomon,com-seq;
+ solomon,com-invdir;
+ solomon,page-offset = <0>;
+ solomon,prechargep1 = <2>;
+ solomon,prechargep2 = <13>;
+ };
};
&spi0 {
diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi
index 3a8a205c27b5..4e2986f0c604 100644
--- a/arch/arm/boot/dts/am33xx-l4.dtsi
+++ b/arch/arm/boot/dts/am33xx-l4.dtsi
@@ -225,7 +225,6 @@
target-module@d000 { /* 0x44e0d000, ap 20 38.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "adc_tsc";
reg = <0xd000 0x4>,
<0xd010 0x4>;
reg-names = "rev", "sysc";
@@ -1009,7 +1008,6 @@
target-module@30000 { /* 0x48030000, ap 77 08.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "spi0";
reg = <0x30000 0x4>,
<0x30110 0x4>,
<0x30114 0x4>;
@@ -1134,7 +1132,6 @@
target-module@42000 { /* 0x48042000, ap 24 1c.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer3";
reg = <0x42000 0x4>,
<0x42010 0x4>,
<0x42014 0x4>;
@@ -1160,7 +1157,6 @@
target-module@44000 { /* 0x48044000, ap 26 26.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer4";
reg = <0x44000 0x4>,
<0x44010 0x4>,
<0x44014 0x4>;
@@ -1187,7 +1183,6 @@
target-module@46000 { /* 0x48046000, ap 28 28.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer5";
reg = <0x46000 0x4>,
<0x46010 0x4>,
<0x46014 0x4>;
@@ -1214,7 +1209,6 @@
target-module@48000 { /* 0x48048000, ap 30 22.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer6";
reg = <0x48000 0x4>,
<0x48010 0x4>,
<0x48014 0x4>;
@@ -1241,7 +1235,6 @@
target-module@4a000 { /* 0x4804a000, ap 85 60.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer7";
reg = <0x4a000 0x4>,
<0x4a010 0x4>,
<0x4a014 0x4>;
@@ -1344,7 +1337,6 @@
target-module@80000 { /* 0x48080000, ap 38 18.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "elm";
reg = <0x80000 0x4>,
<0x80010 0x4>,
<0x80014 0x4>;
@@ -1412,7 +1404,6 @@
target-module@ca000 { /* 0x480ca000, ap 91 40.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "spinlock";
reg = <0xca000 0x4>,
<0xca010 0x4>,
<0xca014 0x4>;
@@ -1533,7 +1524,6 @@
target-module@a0000 { /* 0x481a0000, ap 79 24.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "spi1";
reg = <0xa0000 0x4>,
<0xa0110 0x4>,
<0xa0114 0x4>;
@@ -1749,7 +1739,6 @@
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xcc020 0x4>;
reg-names = "rev";
- ti,hwmods = "d_can0";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>,
<&dcan0_fck>;
@@ -1773,7 +1762,6 @@
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xd0020 0x4>;
reg-names = "rev";
- ti,hwmods = "d_can1";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>,
<&dcan1_fck>;
@@ -1863,7 +1851,6 @@
target-module@0 { /* 0x48300000, ap 66 48.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "epwmss0";
reg = <0x0 0x4>,
<0x4 0x4>;
reg-names = "rev", "sysc";
@@ -1916,7 +1903,6 @@
target-module@2000 { /* 0x48302000, ap 68 52.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "epwmss1";
reg = <0x2000 0x4>,
<0x2004 0x4>;
reg-names = "rev", "sysc";
@@ -1969,7 +1955,6 @@
target-module@4000 { /* 0x48304000, ap 70 44.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "epwmss2";
reg = <0x4000 0x4>,
<0x4004 0x4>;
reg-names = "rev", "sysc";
@@ -2022,7 +2007,6 @@
target-module@e000 { /* 0x4830e000, ap 72 4a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "lcdc";
reg = <0xe000 0x4>,
<0xe054 0x4>;
reg-names = "rev", "sysc";
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 646f11430dad..e403fb765e70 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -439,23 +439,62 @@
status = "disabled";
};
- sham: sham@53100000 {
- compatible = "ti,omap4-sham";
- ti,hwmods = "sham";
- reg = <0x53100000 0x200>;
- interrupts = <109>;
- dmas = <&edma 36 0>;
- dma-names = "rx";
+ sham_target: target-module@53100000 {
+ compatible = "ti,sysc-omap3-sham", "ti,sysc";
+ reg = <0x53100100 0x4>,
+ <0x53100110 0x4>,
+ <0x53100114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l3_clkdm */
+ clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x53100000 0x1000>;
+
+ sham: sham@0 {
+ compatible = "ti,omap4-sham";
+ reg = <0 0x200>;
+ interrupts = <109>;
+ dmas = <&edma 36 0>;
+ dma-names = "rx";
+ };
};
- aes: aes@53500000 {
- compatible = "ti,omap4-aes";
- ti,hwmods = "aes";
- reg = <0x53500000 0xa0>;
- interrupts = <103>;
- dmas = <&edma 6 0>,
- <&edma 5 0>;
- dma-names = "tx", "rx";
+ aes_target: target-module@53500000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x53500080 0x4>,
+ <0x53500084 0x4>,
+ <0x53500088 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l3_clkdm */
+ clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x53500000 0x1000>;
+
+ aes: aes@0 {
+ compatible = "ti,omap4-aes";
+ reg = <0 0xa0>;
+ interrupts = <103>;
+ dmas = <&edma 6 0>,
+ <&edma 5 0>;
+ dma-names = "tx", "rx";
+ };
};
};
};
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index 125379ecab2f..e0b5a00e2078 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -74,7 +74,7 @@
clock-names = "ick";
};
- davinci_mdio: ethernet@5c030000 {
+ davinci_mdio: mdio@5c030000 {
compatible = "ti,davinci_mdio";
ti,hwmods = "davinci_mdio";
status = "disabled";
diff --git a/arch/arm/boot/dts/am3703.dtsi b/arch/arm/boot/dts/am3703.dtsi
new file mode 100644
index 000000000000..2b994ae790c9
--- /dev/null
+++ b/arch/arm/boot/dts/am3703.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020 André Hentschel <nerv@dawncrow.de>
+ */
+
+#include "omap36xx.dtsi"
+
+&iva {
+ status = "disabled";
+};
+
+&sgx_module {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/am3715.dtsi b/arch/arm/boot/dts/am3715.dtsi
new file mode 100644
index 000000000000..ab328e8c0bd8
--- /dev/null
+++ b/arch/arm/boot/dts/am3715.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020 André Hentschel <nerv@dawncrow.de>
+ */
+
+#include "omap36xx.dtsi"
+
+&iva {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index ca0aa3f26c0a..e4072d0f871a 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -256,33 +256,92 @@
};
};
- sham: sham@53100000 {
- compatible = "ti,omap5-sham";
- ti,hwmods = "sham";
- reg = <0x53100000 0x300>;
- dmas = <&edma 36 0>;
- dma-names = "rx";
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ sham_target: target-module@53100000 {
+ compatible = "ti,sysc-omap3-sham", "ti,sysc";
+ reg = <0x53100100 0x4>,
+ <0x53100110 0x4>,
+ <0x53100114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l3_clkdm */
+ clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x53100000 0x1000>;
+
+ sham: sham@0 {
+ compatible = "ti,omap5-sham";
+ reg = <0 0x300>;
+ dmas = <&edma 36 0>;
+ dma-names = "rx";
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
- aes: aes@53501000 {
- compatible = "ti,omap4-aes";
- ti,hwmods = "aes";
- reg = <0x53501000 0xa0>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&edma 6 0>,
- <&edma 5 0>;
- dma-names = "tx", "rx";
+ aes_target: target-module@53501000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x53501080 0x4>,
+ <0x53501084 0x4>,
+ <0x53501088 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l3_clkdm */
+ clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x53501000 0x1000>;
+
+ aes: aes@0 {
+ compatible = "ti,omap4-aes";
+ reg = <0 0xa0>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&edma 6 0>,
+ <&edma 5 0>;
+ dma-names = "tx", "rx";
+ };
};
- des: des@53701000 {
- compatible = "ti,omap4-des";
- ti,hwmods = "des";
- reg = <0x53701000 0xa0>;
- interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&edma 34 0>,
- <&edma 33 0>;
- dma-names = "tx", "rx";
+ des_target: target-module@53701000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x53701030 0x4>,
+ <0x53701034 0x4>,
+ <0x53701038 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l3_clkdm */
+ clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x53701000 0x1000>;
+
+ des: des@0 {
+ compatible = "ti,omap4-des";
+ reg = <0 0xa0>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&edma 34 0>,
+ <&edma 33 0>;
+ dma-names = "tx", "rx";
+ };
};
gpmc: gpmc@50000000 {
@@ -305,17 +364,34 @@
status = "disabled";
};
- qspi: spi@47900000 {
- compatible = "ti,am4372-qspi";
- reg = <0x47900000 0x100>,
- <0x30000000 0x4000000>;
- reg-names = "qspi_base", "qspi_mmap";
+ target-module@47900000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x47900000 0x4>,
+ <0x47900010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
- #size-cells = <0>;
- ti,hwmods = "qspi";
- interrupts = <0 138 0x4>;
- num-cs = <4>;
- status = "disabled";
+ #size-cells = <1>;
+ ranges = <0x0 0x47900000 0x1000>,
+ <0x30000000 0x30000000 0x4000000>;
+
+ qspi: spi@0 {
+ compatible = "ti,am4372-qspi";
+ reg = <0 0x100>,
+ <0x30000000 0x4000000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ clocks = <&dpll_per_m2_div4_ck>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 138 0x4>;
+ num-cs = <4>;
+ };
};
dss: dss@4832a000 {
diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi
index 0dd59ee14585..e18e17d31272 100644
--- a/arch/arm/boot/dts/am437x-l4.dtsi
+++ b/arch/arm/boot/dts/am437x-l4.dtsi
@@ -225,7 +225,6 @@
target-module@d000 { /* 0x44e0d000, ap 20 38.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "adc_tsc";
reg = <0xd000 0x4>,
<0xd010 0x4>;
reg-names = "rev", "sysc";
@@ -763,7 +762,6 @@
target-module@30000 { /* 0x48030000, ap 65 08.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "spi0";
reg = <0x30000 0x4>,
<0x30110 0x4>,
<0x30114 0x4>;
@@ -900,7 +898,6 @@
target-module@42000 { /* 0x48042000, ap 20 24.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer3";
reg = <0x42000 0x4>,
<0x42010 0x4>,
<0x42014 0x4>;
@@ -927,7 +924,6 @@
target-module@44000 { /* 0x48044000, ap 22 26.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer4";
reg = <0x44000 0x4>,
<0x44010 0x4>,
<0x44014 0x4>;
@@ -955,7 +951,6 @@
target-module@46000 { /* 0x48046000, ap 24 28.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer5";
reg = <0x46000 0x4>,
<0x46010 0x4>,
<0x46014 0x4>;
@@ -983,7 +978,6 @@
target-module@48000 { /* 0x48048000, ap 26 1a.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer6";
reg = <0x48000 0x4>,
<0x48010 0x4>,
<0x48014 0x4>;
@@ -1011,7 +1005,6 @@
target-module@4a000 { /* 0x4804a000, ap 71 48.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer7";
reg = <0x4a000 0x4>,
<0x4a010 0x4>,
<0x4a014 0x4>;
@@ -1107,7 +1100,6 @@
target-module@80000 { /* 0x48080000, ap 32 18.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "elm";
reg = <0x80000 0x4>,
<0x80010 0x4>,
<0x80014 0x4>;
@@ -1169,7 +1161,6 @@
target-module@ca000 { /* 0x480ca000, ap 77 38.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "spinlock";
reg = <0xca000 0x4>,
<0xca010 0x4>,
<0xca014 0x4>;
@@ -1282,7 +1273,6 @@
target-module@a0000 { /* 0x481a0000, ap 67 2c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "spi1";
reg = <0xa0000 0x4>,
<0xa0110 0x4>,
<0xa0114 0x4>;
@@ -1313,7 +1303,6 @@
target-module@a2000 { /* 0x481a2000, ap 69 2e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "spi2";
reg = <0xa2000 0x4>,
<0xa2110 0x4>,
<0xa2114 0x4>;
@@ -1344,7 +1333,6 @@
target-module@a4000 { /* 0x481a4000, ap 92 62.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "spi3";
reg = <0xa4000 0x4>,
<0xa4110 0x4>,
<0xa4114 0x4>;
@@ -1527,7 +1515,6 @@
target-module@c1000 { /* 0x481c1000, ap 94 68.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer8";
reg = <0xc1000 0x4>,
<0xc1010 0x4>,
<0xc1014 0x4>;
@@ -1556,7 +1543,6 @@
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xcc020 0x4>;
reg-names = "rev";
- ti,hwmods = "d_can0";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>;
clock-names = "fck";
@@ -1577,7 +1563,6 @@
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xd0020 0x4>;
reg-names = "rev";
- ti,hwmods = "d_can1";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>;
clock-names = "fck";
@@ -1695,7 +1680,6 @@
target-module@0 { /* 0x48300000, ap 56 40.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "epwmss0";
reg = <0x0 0x4>,
<0x4 0x4>;
reg-names = "rev", "sysc";
@@ -1748,7 +1732,6 @@
target-module@2000 { /* 0x48302000, ap 58 4a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "epwmss1";
reg = <0x2000 0x4>,
<0x2004 0x4>;
reg-names = "rev", "sysc";
@@ -1801,7 +1784,6 @@
target-module@4000 { /* 0x48304000, ap 60 44.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "epwmss2";
reg = <0x4000 0x4>,
<0x4004 0x4>;
reg-names = "rev", "sysc";
@@ -1854,7 +1836,6 @@
target-module@6000 { /* 0x48306000, ap 96 58.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "epwmss3";
reg = <0x6000 0x4>,
<0x6004 0x4>;
reg-names = "rev", "sysc";
@@ -1896,7 +1877,6 @@
target-module@8000 { /* 0x48308000, ap 98 54.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "epwmss4";
reg = <0x8000 0x4>,
<0x8004 0x4>;
reg-names = "rev", "sysc";
@@ -1938,7 +1918,6 @@
target-module@a000 { /* 0x4830a000, ap 100 60.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "epwmss5";
reg = <0xa000 0x4>,
<0xa004 0x4>;
reg-names = "rev", "sysc";
@@ -2086,7 +2065,6 @@
target-module@26000 { /* 0x48326000, ap 86 66.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "vpfe0";
reg = <0x26000 0x4>,
<0x26104 0x4>;
reg-names = "rev", "sysc";
@@ -2113,7 +2091,6 @@
target-module@28000 { /* 0x48328000, ap 75 0e.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "vpfe1";
reg = <0x28000 0x4>,
<0x28104 0x4>;
reg-names = "rev", "sysc";
@@ -2162,7 +2139,6 @@
target-module@3d000 { /* 0x4833d000, ap 102 6e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer9";
reg = <0x3d000 0x4>,
<0x3d010 0x4>,
<0x3d014 0x4>;
@@ -2189,7 +2165,6 @@
target-module@3f000 { /* 0x4833f000, ap 104 5c.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer10";
reg = <0x3f000 0x4>,
<0x3f010 0x4>,
<0x3f014 0x4>;
@@ -2216,7 +2191,6 @@
target-module@41000 { /* 0x48341000, ap 106 76.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer11";
reg = <0x41000 0x4>,
<0x41010 0x4>,
<0x41014 0x4>;
@@ -2243,7 +2217,6 @@
target-module@45000 { /* 0x48345000, ap 108 6a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "spi4";
reg = <0x45000 0x4>,
<0x45110 0x4>,
<0x45114 0x4>;
@@ -2358,7 +2331,6 @@
target-module@a8000 { /* 0x483a8000, ap 125 6c.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "ocp2scp0";
reg = <0xa8000 0x4>;
reg-names = "rev";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
@@ -2440,7 +2412,6 @@
target-module@e8000 { /* 0x483e8000, ap 129 78.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "ocp2scp1";
reg = <0xe8000 0x4>;
reg-names = "rev";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi
index 398721c7201c..aa5e55f98179 100644
--- a/arch/arm/boot/dts/am57xx-idk-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi
@@ -9,6 +9,7 @@
aliases {
rtc0 = &tps659038_rtc;
rtc1 = &rtc;
+ display0 = &hdmi0;
};
chosen {
@@ -96,6 +97,48 @@
default-state = "off";
};
};
+
+ hdmi0: connector@0 {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&tpd12s015_out>;
+ };
+ };
+ };
+
+ tpd12s015: encoder@0 {
+ compatible = "ti,tpd12s016", "ti,tpd12s015";
+
+ gpios = <0>, /* optional CT_CP_HPD */
+ <0>, /* optional LS_OE */
+ <&gpio7 12 GPIO_ACTIVE_HIGH>; /* HPD */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpd12s015_in: endpoint@0 {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpd12s015_out: endpoint@0 {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
};
&dra7_pmx_core {
@@ -485,3 +528,19 @@
&cpu0 {
vdd-supply = <&smps12_reg>;
};
+
+&hdmi {
+ status = "okay";
+
+ vdda-supply = <&ldo4_reg>;
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&tpd12s015_in>;
+ };
+ };
+};
+
+&dss {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts b/arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts
new file mode 100644
index 000000000000..c9ac630e5874
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include "armada-385-clearfog-gtr.dtsi"
+
+/ {
+ model = "SolidRun Clearfog GTR L8";
+};
+
+&mdio {
+ switch0: switch0@4 {
+ compatible = "marvell,mv88e6190";
+ reg = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cf_gtr_switch_reset_pins>;
+ reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ label = "lan8";
+ phy-handle = <&switch0phy0>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan7";
+ phy-handle = <&switch0phy1>;
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan6";
+ phy-handle = <&switch0phy2>;
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan5";
+ phy-handle = <&switch0phy3>;
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "lan4";
+ phy-handle = <&switch0phy4>;
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "lan3";
+ phy-handle = <&switch0phy5>;
+ };
+
+ port@7 {
+ reg = <7>;
+ label = "lan2";
+ phy-handle = <&switch0phy6>;
+ };
+
+ port@8 {
+ reg = <8>;
+ label = "lan1";
+ phy-handle = <&switch0phy7>;
+ };
+
+ port@10 {
+ reg = <10>;
+ label = "cpu";
+ ethernet = <&eth1>;
+ };
+
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0phy0: switch0phy0@1 {
+ reg = <0x1>;
+ };
+
+ switch0phy1: switch0phy1@2 {
+ reg = <0x2>;
+ };
+
+ switch0phy2: switch0phy2@3 {
+ reg = <0x3>;
+ };
+
+ switch0phy3: switch0phy3@4 {
+ reg = <0x4>;
+ };
+
+ switch0phy4: switch0phy4@5 {
+ reg = <0x5>;
+ };
+
+ switch0phy5: switch0phy5@6 {
+ reg = <0x6>;
+ };
+
+ switch0phy6: switch0phy6@7 {
+ reg = <0x7>;
+ };
+
+ switch0phy7: switch0phy7@8 {
+ reg = <0x8>;
+ };
+ };
+
+ };
+};
diff --git a/arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts b/arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts
new file mode 100644
index 000000000000..fa653b379490
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include "armada-385-clearfog-gtr.dtsi"
+
+/ {
+ model = "SolidRun Clearfog GTR S4";
+};
+
+&sfp0 {
+ tx-fault-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
+};
+
+&mdio {
+ switch0: switch0@4 {
+ compatible = "marvell,mv88e6085";
+ reg = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cf_gtr_switch_reset_pins>;
+ reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ phy-handle = <&switch0phy0>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan1";
+ phy-handle = <&switch0phy1>;
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ phy-handle = <&switch0phy2>;
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan3";
+ phy-handle = <&switch0phy3>;
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&eth1>;
+ };
+
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0phy0: switch0phy0@11 {
+ reg = <0x11>;
+ };
+
+ switch0phy1: switch0phy1@12 {
+ reg = <0x12>;
+ };
+
+ switch0phy2: switch0phy2@13 {
+ reg = <0x13>;
+ };
+
+ switch0phy3: switch0phy3@14 {
+ reg = <0x14>;
+ };
+ };
+
+ };
+};
diff --git a/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi b/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi
new file mode 100644
index 000000000000..624bbcae68c0
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi
@@ -0,0 +1,450 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Device Tree file for Clearfog GTR machines rev 1.0 (88F6825)
+ *
+ * Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
+ */
+
+/*
+ SERDES mapping -
+ 0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
+ 1. 6141 switch (2.5Gbps capable)
+ 2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
+ 3. USB 3.0 Host
+ 4. mini PCIe CON2 - PCIe2
+ 5. SFP connector, or optionally SGMII Ethernet 1512 PHY
+
+ USB 2.0 mapping -
+ 0. USB 2.0 - 0 USB pins header CON12
+ 1. USB 2.0 - 1 mini PCIe CON2
+ 2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3)
+
+ Pin mapping -
+ 0,1 - console UART
+ 2,3 - I2C0 - connected to I2C EEPROM, two temperature sensors,
+ front panel and PSE controller
+ 4,5 - MDC/MDIO
+ 6..17 - RGMII
+ 18 - Topaz switch reset (active low)
+ 19 - 1512 phy reset
+ 20 - 1512 phy reset (eth2, optional)
+ 21,28,37,38,39,40 - SD0
+ 22 - USB 3.0 current limiter enable (active high)
+ 24 - SFP TX fault (input active high)
+ 25 - SFP present (input active low)
+ 26,27 - I2C1 - connected to SFP
+ 29 - Fan PWM
+ 30 - CON4 mini PCIe wifi disable
+ 31 - CON3 mini PCIe wifi disable
+ 32 - Fuse programming power toggle (1.8v)
+ 33 - CON4 mini PCIe reset
+ 34 - CON2 mini PCIe wifi disable
+ 35 - CON3 mini PCIe reset
+ 36 - Rear button (GPIO active low)
+ 41 - CON1 front panel connector
+ 42 - Front LED1, or front panel CON1
+ 43 - Micron L-PBGA 24 ball SPI (1Gb) CS, or TPM SPI CS
+ 44 - CON2 mini PCIe reset
+ 45 - TPM PIRQ signal, or front panel CON1
+ 46 - SFP TX disable
+ 47 - Control isolation of boot sensitive SAR signals
+ 48 - PSE reset
+ 49 - PSE OSS signal
+ 50 - PSE interrupt
+ 52 - Front LED2, or front panel
+ 53 - Front button
+ 54 - SFP LOS (input active high)
+ 55 - Fan sense
+ 56(mosi),57(clk),58(miso) - SPI interface - 32Mb SPI, 1Gb SPI and TPM
+ 59 - SPI 32Mb W25Q32BVZPIG CS0 chip select (bootable)
+*/
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include "armada-385.dtsi"
+
+/ {
+ compatible = "marvell,armada385", "marvell,armada380";
+
+ aliases {
+ /* So that mvebu u-boot can update the MAC addresses */
+ ethernet1 = &eth0;
+ ethernet2 = &eth1;
+ ethernet3 = &eth2;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>; /* 256 MB */
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_5p0v: regulator-5p0v {
+ compatible = "regulator-fixed";
+ regulator-name = "5P0V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ v_usb3_con: regulator-v-usb3-con {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 22 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cf_gtr_usb3_con_vbus>;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "v_usb3_con";
+ vin-supply = <&reg_5p0v>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
+ MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
+ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
+ MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
+
+ internal-regs {
+
+ rtc@a3800 {
+ status = "okay";
+ };
+
+ i2c@11000 { /* ROM, temp sensor and front panel */
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ i2c@11100 { /* SFP (CON5/CON6) */
+ pinctrl-0 = <&cf_gtr_i2c1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ pinctrl@18000 {
+ cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins {
+ marvell,pins = "mpp18";
+ marvell,function = "gpio";
+ };
+
+ cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus {
+ marvell,pins = "mpp22";
+ marvell,function = "gpio";
+ };
+
+ cf_gtr_fan_pwm: cf-gtr-fan-pwm {
+ marvell,pins = "mpp23";
+ marvell,function = "gpio";
+ };
+
+ cf_gtr_i2c1_pins: i2c1-pins {
+ /* SFP */
+ marvell,pins = "mpp26", "mpp27";
+ marvell,function = "i2c1";
+ };
+
+ cf_gtr_sdhci_pins: cf-gtr-sdhci-pins {
+ marvell,pins = "mpp21", "mpp28",
+ "mpp37", "mpp38",
+ "mpp39", "mpp40";
+ marvell,function = "sd0";
+ };
+
+ cf_gtr_isolation_pins: cf-gtr-isolation-pins {
+ marvell,pins = "mpp47";
+ marvell,function = "gpio";
+ };
+
+ cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins {
+ marvell,pins = "mpp48";
+ marvell,function = "gpio";
+ };
+
+ cf_gtr_spi1_cs_pins: spi1-cs-pins {
+ marvell,pins = "mpp59";
+ marvell,function = "spi1";
+ };
+
+ cf_gtr_front_button_pins: cf-gtr-front-button-pins {
+ marvell,pins = "mpp53";
+ marvell,function = "gpio";
+ };
+
+ cf_gtr_rear_button_pins: cf-gtr-rear-button-pins {
+ marvell,pins = "mpp36";
+ marvell,function = "gpio";
+ };
+ };
+
+ sdhci@d8000 {
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+ pinctrl-0 = <&cf_gtr_sdhci_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ vmmc = <&reg_3p3v>;
+ wp-inverted;
+ };
+
+ usb@58000 {
+ status = "okay";
+ };
+
+ usb3@f0000 {
+ status = "okay";
+ };
+
+ usb3@f8000 {
+ vbus-supply = <&v_usb3_con>;
+ status = "okay";
+ };
+ };
+
+ pcie {
+ status = "okay";
+ /*
+ * The PCIe units are accessible through
+ * the mini-PCIe connectors on the board.
+ */
+ pcie@1,0 {
+ reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ status = "okay";
+ };
+
+ pcie@2,0 {
+ reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+ status = "okay";
+ };
+
+ pcie@3,0 {
+ reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+ status = "okay";
+ };
+ };
+ };
+
+ sfp0: sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&cf_gtr_rear_button_pins &cf_gtr_front_button_pins>;
+ pinctrl-names = "default";
+
+ button_0 {
+ label = "Rear Button";
+ gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ linux,can-disable;
+ linux,code = <BTN_0>;
+ };
+
+ button_1 {
+ label = "Front Button";
+ gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
+ linux,can-disable;
+ linux,code = <BTN_1>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ led1 {
+ function = LED_FUNCTION_CPU;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ };
+
+ led2 {
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&bm {
+ status = "okay";
+};
+
+&bm_bppi {
+ status = "okay";
+};
+
+&eth0 {
+ /* ethernet@70000 */
+ pinctrl-0 = <&ge0_rgmii_pins>;
+ pinctrl-names = "default";
+ phy = <&phy_dedicated>;
+ phy-mode = "rgmii-id";
+ buffer-manager = <&bm>;
+ bm,pool-long = <0>;
+ bm,pool-short = <1>;
+ status = "okay";
+};
+
+&eth1 {
+ /* ethernet@30000 */
+ bm,pool-long = <2>;
+ bm,pool-short = <1>;
+ buffer-manager = <&bm>;
+ phys = <&comphy1 1>;
+ phy-mode = "2500base-x";
+ status = "okay";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ };
+};
+
+&eth2 {
+ /* ethernet@34000 */
+ bm,pool-long = <3>;
+ bm,pool-short = <1>;
+ buffer-manager = <&bm>;
+ managed = "in-band-status";
+ phys = <&comphy5 1>;
+ phy-mode = "sgmii";
+ sfp = <&sfp0>;
+ status = "okay";
+};
+
+&mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio_pins>;
+ status = "okay";
+
+ phy_dedicated: ethernet-phy@0 {
+ /*
+ * Annoyingly, the marvell phy driver configures the LED
+ * register, rather than preserving reset-loaded setting.
+ * We undo that rubbish here.
+ */
+ marvell,reg-init = <3 16 0 0x1017>;
+ reg = <0>;
+ };
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&spi1 {
+ /*
+ * CS0: W25Q32 flash
+ */
+ pinctrl-0 = <&spi1_pins &cf_gtr_spi1_cs_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "w25q32", "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <3000000>;
+ status = "okay";
+ };
+};
+
+&i2c0 {
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /* U26 temperature sensor placed near SoC */
+ temp1: nct75@4c {
+ compatible = "lm75";
+ reg = <0x4c>;
+ };
+
+ /* U27 temperature sensor placed near RTC battery */
+ temp2: nct75@4d {
+ compatible = "lm75";
+ reg = <0x4d>;
+ };
+
+ /* 2Kb eeprom */
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ };
+};
+
+&ahci0 {
+ status = "okay";
+};
+
+&ahci1 {
+ status = "okay";
+};
+
+&gpio0 {
+ pinctrl-0 = <&cf_gtr_fan_pwm>;
+ pinctrl-names = "default";
+
+ wifi-disable {
+ gpio-hog;
+ gpios = <30 GPIO_ACTIVE_LOW>, <31 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "wifi-disable";
+ };
+};
+
+&gpio1 {
+ pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>;
+ pinctrl-names = "default";
+
+ lte-disable {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "lte-disable";
+ };
+
+ /*
+ * This signal, when asserted, isolates Armada 38x sample at reset pins
+ * from control of external devices. Should be de-asserted after reset.
+ */
+ sar-isolation {
+ gpio-hog;
+ gpios = <15 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "sar-isolation";
+ };
+
+ poe-reset {
+ gpio-hog;
+ gpios = <16 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "poe-reset";
+ };
+};
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dtsi b/arch/arm/boot/dts/armada-388-clearfog.dtsi
index 0d81600ca247..a0aa1d188f0c 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dtsi
+++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi
@@ -111,11 +111,6 @@
};
&i2c0 {
- clock-frequency = <400000>;
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
/*
* PCA9655 GPIO expander, up to 1MHz clock.
* 0-CON3 CLKREQ#
@@ -183,6 +178,12 @@
compatible = "microchip,mcp3021";
reg = <0x4c>;
};
+
+ eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <16>;
+ };
};
&i2c1 {
diff --git a/arch/arm/boot/dts/armada-388-helios4.dts b/arch/arm/boot/dts/armada-388-helios4.dts
index 705adfa8c680..fb49df2a3bce 100644
--- a/arch/arm/boot/dts/armada-388-helios4.dts
+++ b/arch/arm/boot/dts/armada-388-helios4.dts
@@ -140,11 +140,6 @@
soc {
internal-regs {
i2c@11000 {
- clock-frequency = <400000>;
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
/*
* PCA9655 GPIO expander, up to 1MHz clock.
* 0-Board Revision bit 0 #
diff --git a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
index 3a7f9c1ac346..363ac4238859 100644
--- a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
@@ -71,6 +71,19 @@
};
};
+&i2c0 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
+};
+
&pinctrl {
microsom_phy_clk_pins: microsom-phy-clk-pins {
marvell,pins = "mpp45";
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts
index b1e10f0c85c9..322587b7b67d 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts
@@ -76,7 +76,6 @@
&mac1 {
status = "okay";
- no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts
index aaa77a597d1a..54e508530dce 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts
@@ -75,7 +75,6 @@
&mac1 {
status = "okay";
- no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts
index 52933598aac6..fe2e11c2da15 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts
@@ -35,7 +35,6 @@
&mac0 {
status = "okay";
use-ncsi;
- no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
index 13f7aefe045e..6232cd726a7f 100644
--- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
@@ -97,22 +97,22 @@
status = "okay";
power-supply@68 {
- compatible = "ibm,cffps2";
+ compatible = "ibm,cffps";
reg = <0x68>;
};
power-supply@69 {
- compatible = "ibm,cffps2";
+ compatible = "ibm,cffps";
reg = <0x69>;
};
power-supply@6a {
- compatible = "ibm,cffps2";
+ compatible = "ibm,cffps";
reg = <0x6a>;
};
power-supply@6b {
- compatible = "ibm,cffps2";
+ compatible = "ibm,cffps";
reg = <0x6b>;
};
};
@@ -352,18 +352,8 @@
&i2c8 {
status = "okay";
- ucd90320@b {
- compatible = "ti,ucd90160";
- reg = <0x0b>;
- };
-
- ucd90320@c {
- compatible = "ti,ucd90160";
- reg = <0x0c>;
- };
-
ucd90320@11 {
- compatible = "ti,ucd90160";
+ compatible = "ti,ucd90320";
reg = <0x11>;
};
diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts
index c17bb7fce7ff..62a3ab4c1866 100644
--- a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts
@@ -94,8 +94,6 @@
gpio-keys-polled {
compatible = "gpio-keys-polled";
- #address-cells = <1>;
- #size-cells = <0>;
poll-interval = <1000>;
fan0-presence {
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts
index b8fdd2a8a2c9..d56b5ed09b37 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts
@@ -82,8 +82,6 @@
gpio-keys-polled {
compatible = "gpio-keys-polled";
- #address-cells = <1>;
- #size-cells = <0>;
poll-interval = <1000>;
scm0-presence {
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
index affd2c8743b1..01074b6e3e03 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
@@ -14,7 +14,7 @@
bootargs = "console=ttyS4,115200 earlyprintk";
};
- memory {
+ memory@40000000 {
reg = <0x40000000 0x20000000>;
};
@@ -107,10 +107,7 @@
&mac0 {
status = "okay";
-
use-ncsi;
- no-hw-checksum;
-
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
};
@@ -236,3 +233,16 @@
&wdt2 {
aspeed,alt-boot;
};
+
+&sdmmc {
+ status = "okay";
+};
+
+&sdhci1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sd2_default>;
+ cd-inverted;
+ disable-wp;
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
index 569dad93e162..421aa600148b 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
@@ -77,8 +77,6 @@
gpio-keys-polled {
compatible = "gpio-keys-polled";
- #address-cells = <1>;
- #size-cells = <0>;
poll-interval = <1000>;
fan0-presence {
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 46c0891aac5a..807a0fc20670 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -179,18 +179,21 @@
compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
+ ranges = <0 0x1e6e2000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
- pinctrl: pinctrl {
- compatible = "aspeed,ast2400-pinctrl";
- };
-
- p2a: p2a-control {
+ p2a: p2a-control@2c {
+ reg = <0x2c 0x4>;
compatible = "aspeed,ast2400-p2a-ctrl";
status = "disabled";
};
+
+ pinctrl: pinctrl@80 {
+ reg = <0x80 0x18>, <0xa0 0x10>;
+ compatible = "aspeed,ast2400-pinctrl";
+ };
};
rng: hwrng@1e6e2078 {
@@ -346,14 +349,14 @@
lpc_ctrl: lpc-ctrl@0 {
compatible = "aspeed,ast2400-lpc-ctrl";
- reg = <0x0 0x80>;
+ reg = <0x0 0x10>;
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
- lpc_snoop: lpc-snoop@0 {
+ lpc_snoop: lpc-snoop@10 {
compatible = "aspeed,ast2400-lpc-snoop";
- reg = <0x0 0x80>;
+ reg = <0x10 0x8>;
interrupts = <8>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index a259c63fff06..ebec0fa8baa7 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -47,13 +47,6 @@
reg = <0x80000000 0>;
};
- edac: sdram@1e6e0000 {
- compatible = "aspeed,ast2500-sdram-edac";
- reg = <0x1e6e0000 0x174>;
- interrupts = <0>;
- status = "disabled";
- };
-
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -213,24 +206,33 @@
#size-cells = <1>;
ranges;
+ edac: memory-controller@1e6e0000 {
+ compatible = "aspeed,ast2500-sdram-edac";
+ reg = <0x1e6e0000 0x174>;
+ interrupts = <0>;
+ status = "disabled";
+ };
+
syscon: syscon@1e6e2000 {
compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
+ ranges = <0 0x1e6e2000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
- pinctrl: pinctrl {
- compatible = "aspeed,ast2500-pinctrl";
- aspeed,external-nodes = <&gfx &lhc>;
-
- };
-
- p2a: p2a-control {
+ p2a: p2a-control@2c {
compatible = "aspeed,ast2500-p2a-ctrl";
+ reg = <0x2c 0x4>;
status = "disabled";
};
+
+ pinctrl: pinctrl@80 {
+ compatible = "aspeed,ast2500-pinctrl";
+ reg = <0x80 0x18>, <0xa0 0x10>;
+ aspeed,external-nodes = <&gfx>, <&lhc>;
+ };
};
rng: hwrng@1e6e2078 {
@@ -460,29 +462,30 @@
lpc_ctrl: lpc-ctrl@0 {
compatible = "aspeed,ast2500-lpc-ctrl";
- reg = <0x0 0x80>;
+ reg = <0x0 0x10>;
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
- lpc_snoop: lpc-snoop@0 {
+ lpc_snoop: lpc-snoop@10 {
compatible = "aspeed,ast2500-lpc-snoop";
- reg = <0x0 0x80>;
+ reg = <0x10 0x8>;
interrupts = <8>;
status = "disabled";
};
- lhc: lhc@20 {
- compatible = "aspeed,ast2500-lhc";
- reg = <0x20 0x24 0x48 0x8>;
- };
-
lpc_reset: reset-controller@18 {
compatible = "aspeed,ast2500-lpc-reset";
reg = <0x18 0x4>;
#reset-cells = <1>;
};
+ lhc: lhc@20 {
+ compatible = "aspeed,ast2500-lhc";
+ reg = <0x20 0x24 0x48 0x8>;
+ };
+
+
ibt: ibt@c0 {
compatible = "aspeed,ast2500-ibt-bmc";
reg = <0xc0 0x18>;
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index b72afbaadaf8..796976d275e1 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -365,7 +365,7 @@
status = "disabled";
};
- wdt4: watchdog@1e7850C0 {
+ wdt4: watchdog@1e7850c0 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e7850C0 0x40>;
status = "disabled";
diff --git a/arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi b/arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi
index 7a395ba56512..7468f102bd76 100644
--- a/arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi
+++ b/arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi
@@ -71,7 +71,6 @@
&mac1 {
status = "okay";
- no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
diff --git a/arch/arm/boot/dts/at91-kizbox.dts b/arch/arm/boot/dts/at91-kizbox.dts
index 90996eaf73b2..7d938ccf71b0 100644
--- a/arch/arm/boot/dts/at91-kizbox.dts
+++ b/arch/arm/boot/dts/at91-kizbox.dts
@@ -28,85 +28,6 @@
};
};
- ahb {
- apb {
- tcb0: timer@fffa0000 {
- timer@0 {
- compatible = "atmel,tcb-timer";
- reg = <0>, <1>;
- };
-
- timer@2 {
- compatible = "atmel,tcb-timer";
- reg = <2>;
- };
- };
-
- macb0: ethernet@fffc4000 {
- phy-mode = "mii";
- pinctrl-0 = <&pinctrl_macb_rmii
- &pinctrl_macb_rmii_mii_alt>;
- status = "okay";
- };
-
- usart3: serial@fffd0000 {
- status = "okay";
- };
-
- dbgu: serial@fffff200 {
- status = "okay";
- };
-
- watchdog@fffffd40 {
- timeout-sec = <15>;
- atmel,max-heartbeat-sec = <16>;
- atmel,min-heartbeat-sec = <0>;
- status = "okay";
- };
- };
-
- usb0: ohci@500000 {
- num-ports = <1>;
- status = "okay";
- };
-
- ebi: ebi@10000000 {
- status = "okay";
-
- nand_controller: nand-controller {
- status = "okay";
- pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
- pinctrl-names = "default";
-
- nand@3 {
- reg = <0x3 0x0 0x800000>;
- rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
- cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
- nand-bus-width = <8>;
- nand-ecc-mode = "soft";
- nand-on-flash-bbt;
- label = "atmel_nand";
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- bootstrap@0 {
- label = "bootstrap";
- reg = <0x0 0x20000>;
- };
-
- ubi@20000 {
- label = "ubi";
- reg = <0x20000 0x7fe0000>;
- };
- };
- };
- };
- };
- };
-
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
@@ -127,15 +48,6 @@
};
};
- i2c-gpio-0 {
- status = "okay";
-
- rtc: pcf8563@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- };
- };
-
pwm_leds {
compatible = "pwm-leds";
@@ -179,3 +91,87 @@
&pinctrl_tcb1_tiob0>;
};
};
+
+&tcb0 {
+ timer@0 {
+ compatible = "atmel,tcb-timer";
+ reg = <0>, <1>;
+ };
+
+ timer@2 {
+ compatible = "atmel,tcb-timer";
+ reg = <2>;
+ };
+};
+
+&ebi {
+ status = "okay";
+};
+
+&nand_controller {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
+ pinctrl-names = "default";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "soft";
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootstrap@0 {
+ label = "bootstrap";
+ reg = <0x0 0x20000>;
+ };
+
+ ubi@20000 {
+ label = "ubi";
+ reg = <0x20000 0x7fe0000>;
+ };
+ };
+ };
+};
+
+&macb0 {
+ phy-mode = "mii";
+ pinctrl-0 = <&pinctrl_macb_rmii
+ &pinctrl_macb_rmii_mii_alt>;
+ status = "okay";
+};
+
+&usart3 {
+ status = "okay";
+};
+
+&dbgu {
+ status = "okay";
+};
+
+&watchdog {
+ timeout-sec = <15>;
+ atmel,max-heartbeat-sec = <16>;
+ atmel,min-heartbeat-sec = <0>;
+ status = "okay";
+};
+
+&usb0 {
+ num-ports = <1>;
+ status = "okay";
+};
+
+&i2c_gpio0 {
+ status = "okay";
+
+ rtc: pcf8563@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
diff --git a/arch/arm/boot/dts/at91-kizboxmini-base.dts b/arch/arm/boot/dts/at91-kizboxmini-base.dts
new file mode 100644
index 000000000000..81c29ca5cc1b
--- /dev/null
+++ b/arch/arm/boot/dts/at91-kizboxmini-base.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * at91-kizboxmini-base.dts - Device Tree file for Overkiz Kizbox mini
+ * base board
+ *
+ * Copyright (C) 2015 Overkiz SAS
+ * Author: Antoine Aubert <a.aubert@overkiz.com>
+ * Kévin Raymond <k.raymond@overkiz.com>
+ */
+/dts-v1/;
+#include "at91-kizboxmini-common.dtsi"
+
+/ {
+ model = "Overkiz Kizbox Mini";
+ compatible = "overkiz,kizboxmini-base", "atmel,at91sam9g25",
+ "atmel,at91sam9x5", "atmel,at91sam9";
+};
+
+&pinctrl_usart0 {
+ atmel,pins =
+ <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOA 2 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
+};
diff --git a/arch/arm/boot/dts/at91-kizboxmini.dts b/arch/arm/boot/dts/at91-kizboxmini-common.dtsi
index cb22f5fb055f..fddf267b2d17 100644
--- a/arch/arm/boot/dts/at91-kizboxmini.dts
+++ b/arch/arm/boot/dts/at91-kizboxmini-common.dtsi
@@ -1,17 +1,16 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-License-Identifier: GPL-2.0
/*
* at91-kizboxmini.dts - Device Tree file for Overkiz Kizbox mini board
*
- * Copyright (C) 2014 Gaël PORTAY <g.portay@overkiz.com>
+ * Copyright (C) 2014-2018 Overkiz SAS
+ * Author: Antoine Aubert <a.aubert@overkiz.com>
+ * Gaël Portay <g.portay@overkiz.com>
+ * Kévin Raymond <k.raymond@overkiz.com>
+ * Dorian Rocipon <d.rocipon@overkiz.com>
*/
-/dts-v1/;
#include "at91sam9g25.dtsi"
-#include <dt-bindings/pwm/pwm.h>
/ {
- model = "Overkiz Kizbox mini";
- compatible = "overkiz,kizboxmini", "atmel,at91sam9g25", "atmel,at91sam9x5", "atmel,at91sam9";
-
chosen {
bootargs = "ubi.mtd=ubi";
stdout-path = &dbgu;
@@ -22,24 +21,16 @@
};
clocks {
- slow_xtal {
- clock-frequency = <32768>;
- };
-
main_xtal {
clock-frequency = <12000000>;
};
- };
- ahb {
- nand0: nand@40000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "hw";
- atmel,has-pmecc;
- atmel,pmecc-cap = <4>;
- atmel,pmecc-sector-size = <512>;
- nand-on-flash-bbt;
- status = "okay";
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ adc_op_clk {
+ status = "disabled";
};
};
@@ -63,17 +54,25 @@
};
};
- pwm_leds {
+ leds: pwm_leds {
compatible = "pwm-leds";
- green {
+ led_blue: pwm_blue {
+ label = "pwm:blue:user";
+ pwms = <&pwm0 2 10000000 0>;
+ max-brightness = <255>;
+ linux,default-trigger = "none";
+ status = "disabled";
+ };
+
+ led_green: pwm_green {
label = "pwm:green:user";
pwms = <&pwm0 0 10000000 0>;
max-brightness = <255>;
linux,default-trigger = "default-on";
};
- red {
+ led_red: pwm_red {
label = "pwm:red:user";
pwms = <&pwm0 1 10000000 0>;
max-brightness = <255>;
@@ -82,53 +81,12 @@
};
};
-&dbgu {
+&usart0 {
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
status = "okay";
};
-&ebi {
- pinctrl-0 = <&pinctrl_ebi_addr_nand
- &pinctrl_ebi_data_0_7>;
- pinctrl-names = "default";
- status = "okay";
-
- nand-controller {
- pinctrl-0 = <&pinctrl_nand_oe_we
- &pinctrl_nand_cs
- &pinctrl_nand_rb>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@3 {
- reg = <0x3 0x0 0x800000>;
- rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
- cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
- nand-bus-width = <8>;
- nand-ecc-mode = "hw";
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
- nand-on-flash-bbt;
- label = "atmel_nand";
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- bootstrap@0 {
- label = "bootstrap";
- reg = <0x0 0x20000>;
- };
-
- ubi@20000 {
- label = "ubi";
- reg = <0x20000 0x7fe0000>;
- };
- };
- };
- };
-};
-
&macb0 {
phy-mode = "rmii";
status = "okay";
@@ -137,26 +95,70 @@
&pwm0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_pwm0_1
- &pinctrl_pwm0_pwm1_1>;
+ &pinctrl_pwm0_pwm1_1
+ &pinctrl_pwm0_pwm2_1>;
status = "okay";
};
-&tcb0 {
- timer@0 {
- compatible = "atmel,tcb-timer";
- reg = <0>;
- };
+&dbgu {
+ status = "okay";
+};
- timer@1 {
- compatible = "atmel,tcb-timer";
- reg = <1>;
- };
+&watchdog {
+ status = "okay";
};
-&usart0 {
+&adc0 {
+ status = "disabled";
+};
+
+&rtc {
+ status = "disabled";
+};
+
+&ebi {
+ pinctrl-0 = <&pinctrl_ebi_addr_nand
+ &pinctrl_ebi_data_0_7>;
+ pinctrl-names = "default";
status = "okay";
};
+&nand_controller {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_nand_oe_we
+ &pinctrl_nand_cs
+ &pinctrl_nand_rb>;
+ pinctrl-names = "default";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootstrap@0 {
+ label = "bootstrap";
+ reg = <0x0 0x20000>;
+ };
+
+ ubi@20000 {
+ label = "ubi";
+ reg = <0x20000 0x7fe0000>;
+ };
+ };
+ };
+};
+
&usb0 {
num-ports = <1>;
status = "okay";
@@ -166,6 +168,3 @@
status = "okay";
};
-&watchdog {
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/at91-kizboxmini-mb.dts b/arch/arm/boot/dts/at91-kizboxmini-mb.dts
new file mode 100644
index 000000000000..c07d3076a9bc
--- /dev/null
+++ b/arch/arm/boot/dts/at91-kizboxmini-mb.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015-2018 Overkiz SAS
+ * Author: Mickael Gardet <m.gardet@overkiz.com>
+ * Kévin Raymond <k.raymond@overkiz.com>
+ */
+/dts-v1/;
+#include "at91-kizboxmini-common.dtsi"
+
+/ {
+ model = "Overkiz Kizbox Mini Mother Board";
+ compatible = "overkiz,kizboxmini-mb", "atmel,at91sam9g25",
+ "atmel,at91sam9x5", "atmel,at91sam9";
+};
+
+&usb0 {
+ num-ports = <2>;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&led_blue {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/at91-kizboxmini-rd.dts b/arch/arm/boot/dts/at91-kizboxmini-rd.dts
new file mode 100644
index 000000000000..ab50f4d22387
--- /dev/null
+++ b/arch/arm/boot/dts/at91-kizboxmini-rd.dts
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015-2018 Overkiz SAS
+ * Author: Mickael Gardet <m.gardet@overkiz.com>
+ * Kévin Raymond <k.raymond@overkiz.com>
+ */
+/dts-v1/;
+#include "at91-kizboxmini-common.dtsi"
+
+/ {
+ model = "Overkiz Kizbox Mini RailDIN";
+ compatible = "overkiz,kizboxmini-rd", "atmel,at91sam9g25",
+ "atmel,at91sam9x5", "atmel,at91sam9";
+
+ clocks {
+ adc_op_clk {
+ status = "okay";
+ };
+ };
+};
+
+&pinctrl {
+ adc0 {
+ pinctrl_adc0_ad5: adc0_ad5-0 {
+ /* pull-up disable */
+ atmel,pins = <AT91_PIOB 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ };
+};
+
+&usart0 {
+ status = "disabled";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&led_blue {
+ status = "okay";
+};
+
+&adc0 {
+ atmel,adc-vref = <2500>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc0_ad5>;
+ atmel,adc-channels-used = <0x0020>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
index f245944bd5d7..4f123477e631 100644
--- a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
+++ b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
@@ -8,7 +8,6 @@
*/
/dts-v1/;
#include "at91-linea.dtsi"
-#include "sama5d3_lcd.dtsi"
#include "at91-natte.dtsi"
/ {
diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts
new file mode 100644
index 000000000000..9f30132d7d7b
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sam9x60ek.dts
@@ -0,0 +1,647 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * at91-sam9x60ek.dts - Device Tree file for Microchip SAM9X60-EK board
+ *
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
+ */
+/dts-v1/;
+#include "sam9x60.dtsi"
+
+/ {
+ model = "Microchip SAM9X60-EK";
+ compatible = "microchip,sam9x60ek", "microchip,sam9x60", "atmel,at91sam9";
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ clocks {
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal {
+ clock-frequency = <24000000>;
+ };
+ };
+
+ regulators: regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd_1v8: fixed-regulator-vdd_1v8@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ status = "okay";
+ };
+
+ vdd_1v5: fixed-regulator-vdd_1v5@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_1V5";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ status = "okay";
+ };
+
+ vdd1_3v3: fixed-regulator-vdd1_3v3@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD1_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ status = "okay";
+ };
+
+ vdd2_3v3: regulator-fixed-vdd2_3v3@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD2_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ status = "okay";
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_key_gpio_default>;
+ status = "okay";
+
+ sw1 {
+ label = "SW1";
+ gpios = <&pioD 18 GPIO_ACTIVE_LOW>;
+ linux,code=<0x104>;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ status = "okay"; /* Conflict with pwm0. */
+
+ red {
+ label = "red";
+ gpios = <&pioB 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ green {
+ label = "green";
+ gpios = <&pioB 12 GPIO_ACTIVE_HIGH>;
+ };
+
+ blue {
+ label = "blue";
+ gpios = <&pioB 13 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&adc {
+ vddana-supply = <&vdd1_3v3>;
+ vref-supply = <&vdd1_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>;
+ status = "okay";
+};
+
+&can0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can0_rx_tx>;
+ status = "disabled"; /* Conflict with dbgu. */
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_rx_tx>;
+ status = "okay";
+};
+
+&classd {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_classd_default>;
+ atmel,pwm-type = "diff";
+ atmel,non-overlap-time = <10>;
+ status = "okay";
+};
+
+&dbgu {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dbgu>;
+ status = "okay"; /* Conflict with can0. */
+};
+
+&ebi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
+ status = "okay";
+
+ nand_controller: nand-controller {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>;
+ status = "okay";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ uboot@40000 {
+ label = "u-boot";
+ reg = <0x40000 0xc0000>;
+ };
+
+ ubootenvred@100000 {
+ label = "U-Boot Env Redundant";
+ reg = <0x100000 0x40000>;
+ };
+
+ ubootenv@140000 {
+ label = "U-Boot Env";
+ reg = <0x140000 0x40000>;
+ };
+
+ dtb@180000 {
+ label = "device tree";
+ reg = <0x180000 0x80000>;
+ };
+
+ kernel@200000 {
+ label = "kernel";
+ reg = <0x200000 0x600000>;
+ };
+
+ rootfs@800000 {
+ label = "rootfs";
+ reg = <0x800000 0x1f800000>;
+ };
+ };
+ };
+ };
+};
+
+&flx0 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+ status = "okay";
+
+ i2c0: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx0_default>;
+ atmel,fifo-size = <16>;
+ i2c-analog-filter;
+ i2c-digital-filter;
+ i2c-digital-filter-width-ns = <35>;
+ status = "okay";
+
+ eeprom@53 {
+ compatible = "atmel,24c32";
+ reg = <0x53>;
+ pagesize = <16>;
+ size = <128>;
+ status = "okay";
+ };
+ };
+};
+
+&flx4 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
+ status = "disabled";
+
+ spi0: spi@400 {
+ compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+ clock-names = "spi_clk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx4_default>;
+ atmel,fifo-size = <16>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+};
+
+&flx5 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+ status = "okay";
+
+ uart1: serial@200 {
+ compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(10))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(11))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+ clock-names = "usart";
+ pinctrl-0 = <&pinctrl_flx5_default>;
+ pinctrl-names = "default";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "okay";
+ };
+};
+
+&flx6 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+ status = "okay";
+
+ i2c1: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx6_default>;
+ atmel,fifo-size = <16>;
+ i2c-analog-filter;
+ i2c-digital-filter;
+ i2c-digital-filter-width-ns = <35>;
+ status = "okay";
+
+ gpio_exp: mcp23008@20 {
+ compatible = "microchip,mcp23008";
+ reg = <0x20>;
+ };
+ };
+};
+
+&i2s {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2s_default>;
+ #sound-dai-cells = <0>;
+ status = "disabled"; /* Conflict with QSPI. */
+};
+
+&macb0 {
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_rmii>;
+ status = "okay";
+
+ ethernet-phy@0 {
+ reg = <0x0>;
+ };
+};
+
+&pinctrl {
+ atmel,mux-mask = <
+ /* A B C */
+ 0xFFFFFE7F 0xC0E0397F 0xEF00019D /* pioA */
+ 0x03FFFFFF 0x02FC7E68 0x00780000 /* pioB */
+ 0xffffffff 0xF83FFFFF 0xB800F3FC /* pioC */
+ 0x003FFFFF 0x003F8000 0x00000000 /* pioD */
+ >;
+
+ adc {
+ pinctrl_adc_default: adc_default {
+ atmel,pins = <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_adtrg_default: adtrg_default {
+ atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
+ };
+ };
+
+ dbgu {
+ pinctrl_dbgu: dbgu-0 {
+ atmel,pins = <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ };
+
+ i2s {
+ pinctrl_i2s_default: i2s {
+ atmel,pins =
+ <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* I2SCK */
+ AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* I2SWS */
+ AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* I2SDIN */
+ AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* I2SDOUT */
+ AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* I2SMCK */
+ };
+ };
+
+ qspi {
+ pinctrl_qspi: qspi {
+ atmel,pins =
+ <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_SLEWRATE_DIS
+ AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_SLEWRATE_DIS
+ AT91_PIOB 21 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOB 22 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOB 23 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOB 24 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)>;
+ };
+ };
+
+ nand {
+ pinctrl_nand_oe_we: nand-oe-we-0 {
+ atmel,pins =
+ <AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+ };
+
+ pinctrl_nand_rb: nand-rb-0 {
+ atmel,pins =
+ <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+ };
+
+ pinctrl_nand_cs: nand-cs-0 {
+ atmel,pins =
+ <AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+ };
+ };
+
+ ebi {
+ pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
+ atmel,pins =
+ <AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+ };
+
+ pinctrl_ebi_data_0_15: ebi-data-msb-0 {
+ atmel,pins =
+ <AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_addr_nand: ebi-addr-0 {
+ atmel,pins =
+ <AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+ };
+ };
+
+ flexcom {
+ pinctrl_flx0_default: flx0_twi {
+ atmel,pins =
+ <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+ };
+
+ pinctrl_flx4_default: flx4_spi {
+ atmel,pins =
+ <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_flx5_default: flx_uart {
+ atmel,pins =
+ <AT91_PIOA 7 AT91_PERIPH_C AT91_PINCTRL_NONE
+ AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE
+ AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE
+ AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_flx6_default: flx6_twi {
+ atmel,pins =
+ <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+ };
+ };
+
+ classd {
+ pinctrl_classd_default: classd {
+ atmel,pins =
+ <AT91_PIOA 24 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
+ AT91_PIOA 25 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
+ AT91_PIOA 26 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
+ AT91_PIOA 27 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;
+ };
+ };
+
+ can0 {
+ pinctrl_can0_rx_tx: can0_rx_tx {
+ atmel,pins =
+ <AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX0 */
+ AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANTX0 */
+ AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN /* Enable CAN0 mux */
+ AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN>; /* Enable CAN Transceivers */
+ };
+ };
+
+ can1 {
+ pinctrl_can1_rx_tx: can1_rx_tx {
+ atmel,pins =
+ <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX1 RXD1 */
+ AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANTX1 TXD1 */
+ AT91_PIOD 19 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN /* Enable CAN1 mux */
+ AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN>; /* Enable CAN Transceivers */
+ };
+ };
+
+ macb0 {
+ pinctrl_macb0_rmii: macb0_rmii-0 {
+ atmel,pins =
+ <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
+ AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
+ AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
+ AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
+ AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
+ AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
+ AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
+ AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
+ AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
+ AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
+ };
+ };
+
+ pwm0 {
+ pinctrl_pwm0_0: pwm0_0 {
+ atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_pwm0_1: pwm0_1 {
+ atmel,pins = <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_pwm0_2: pwm0_2 {
+ atmel,pins = <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_pwm0_3: pwm0_3 {
+ atmel,pins = <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ };
+
+ sdmmc0 {
+ pinctrl_sdmmc0_default: sdmmc0 {
+ atmel,pins =
+ <AT91_PIOA 17 AT91_PERIPH_A (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA17 CK periph A with pullup */
+ AT91_PIOA 16 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA16 CMD periph A with pullup */
+ AT91_PIOA 15 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA15 DAT0 periph A */
+ AT91_PIOA 18 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA18 DAT1 periph A with pullup */
+ AT91_PIOA 19 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA19 DAT2 periph A with pullup */
+ AT91_PIOA 20 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA20 DAT3 periph A with pullup */
+ };
+ };
+
+ gpio_keys {
+ pinctrl_key_gpio_default: pinctrl_key_gpio {
+ atmel,pins = <AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ };
+}; /* pinctrl */
+
+&pmc {
+ atmel,osc-bypass;
+};
+
+&pwm0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2 &pinctrl_pwm0_3>;
+ status = "disabled"; /* Conflict with leds. */
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc0_default>;
+ status = "okay";
+ cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
+ disable-wp;
+};
+
+&qspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi>;
+ status = "okay"; /* Conflict with i2s. */
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <80000000>;
+ m25p,fast-read;
+
+ at91bootstrap@0 {
+ label = "qspi: at91bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ bootloader@40000 {
+ label = "qspi: bootloader";
+ reg = <0x40000 0xc0000>;
+ };
+
+ bootloaderenvred@100000 {
+ label = "qspi: bootloader env redundant";
+ reg = <0x100000 0x40000>;
+ };
+
+ bootloaderenv@140000 {
+ label = "qspi: bootloader env";
+ reg = <0x140000 0x40000>;
+ };
+
+ dtb@180000 {
+ label = "qspi: device tree";
+ reg = <0x180000 0x80000>;
+ };
+
+ kernel@200000 {
+ label = "qspi: kernel";
+ reg = <0x200000 0x600000>;
+ };
+ };
+};
+
+&shutdown_controller {
+ atmel,shdwc-debouncer = <976>;
+ status = "okay";
+
+ input@0 {
+ reg = <0>;
+ };
+};
+
+&tcb0 {
+ timer0: timer@0 {
+ compatible = "atmel,tcb-timer";
+ reg = <0>;
+ };
+
+ timer1: timer@1 {
+ compatible = "atmel,tcb-timer";
+ reg = <1>;
+ };
+};
+
+&usb1 {
+ num-ports = <3>;
+ atmel,vbus-gpio = <0
+ &pioD 15 GPIO_ACTIVE_HIGH
+ &pioD 16 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
index 7788d5db65c2..6281590150c8 100644
--- a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
+++ b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
@@ -24,6 +24,10 @@
};
ahb {
+ sdmmc0: sdio-host@a0000000 {
+ microchip,sdcal-inverted;
+ };
+
apb {
qspi1: spi@f0024000 {
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
index fca5716ce44f..b0853bf7901c 100644
--- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
@@ -131,6 +131,9 @@
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <0>, <0>;
dma-names = "tx", "rx";
+ i2c-analog-filter;
+ i2c-digital-filter;
+ i2c-digital-filter-width-ns = <35>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
@@ -246,6 +249,9 @@
i2c1: i2c@fc028000 {
dmas = <0>, <0>;
+ i2c-analog-filter;
+ i2c-digital-filter;
+ i2c-digital-filter-width-ns = <35>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_default>;
status = "okay";
diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
new file mode 100644
index 000000000000..db3e2239eee8
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
@@ -0,0 +1,304 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * at91-sama5d27_wlsom1.dtsi - Device Tree file for SAMA5D27 WLSOM1
+ *
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
+ * Author: Eugen Hristev <eugen.hristev@microcihp.com>
+ */
+#include "sama5d2.dtsi"
+#include "sama5d2-pinfunc.h"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mfd/atmel-flexcom.h>
+#include <dt-bindings/pinctrl/at91.h>
+
+/ {
+ model = "Microchip SAMA5D27 WLSOM1";
+ compatible = "microchip,sama5d27-wlsom1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
+
+ clocks {
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal {
+ clock-frequency = <24000000>;
+ };
+ };
+};
+
+&flx1 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+
+ uart6: serial@200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(13))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(14))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
+ clock-names = "usart";
+ pinctrl-0 = <&pinctrl_flx1_default>;
+ pinctrl-names = "default";
+ };
+};
+
+&i2c0 {
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&i2c1 {
+ dmas = <0>, <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ status = "okay";
+
+ mcp16502@5b {
+ compatible = "microchip,mcp16502";
+ reg = <0x5b>;
+ status = "okay";
+ lpm-gpios = <&pioBU 0 GPIO_ACTIVE_LOW>;
+
+ regulators {
+ vdd_3v3: VDD_IO {
+ regulator-name = "VDD_IO";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-initial-mode = <2>;
+ regulator-allowed-modes = <2>, <4>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ regulator-mode = <4>;
+ };
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-mode = <4>;
+ };
+ };
+
+ vddio_ddr: VDD_DDR {
+ regulator-name = "VDD_DDR";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1850000>;
+ regulator-initial-mode = <2>;
+ regulator-allowed-modes = <2>, <4>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1200000>;
+ regulator-changeable-in-suspend;
+ regulator-mode = <4>;
+ };
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1200000>;
+ regulator-changeable-in-suspend;
+ regulator-mode = <4>;
+ };
+ };
+
+ vdd_core: VDD_CORE {
+ regulator-name = "VDD_CORE";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1850000>;
+ regulator-initial-mode = <2>;
+ regulator-allowed-modes = <2>, <4>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ regulator-mode = <4>;
+ };
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-mode = <4>;
+ };
+ };
+
+ vdd_ddr: VDD_OTHER {
+ regulator-name = "VDD_OTHER";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <2>;
+ regulator-allowed-modes = <2>, <4>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ regulator-changeable-in-suspend;
+ regulator-mode = <4>;
+ };
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ regulator-changeable-in-suspend;
+ regulator-mode = <4>;
+ };
+ };
+
+ LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ };
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ LDO2 {
+ regulator-name = "LDO2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ };
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&macb0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_default>;
+ phy-mode = "rmii";
+
+ ethernet-phy@0 {
+ reg = <0x0>;
+ interrupt-parent = <&pioA>;
+ interrupts = <PIN_PB24 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_phy_irq>;
+ };
+};
+
+&pmc {
+ atmel,osc-bypass;
+};
+
+&qspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi1_default>;
+ status = "disabled";
+
+ qspi1_flash: spi_flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <80000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ m25p,fast-read;
+ status = "disabled";
+
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ bootloader@40000 {
+ label = "bootloader";
+ reg = <0x40000 0xc0000>;
+ };
+
+ bootloaderenvred@100000 {
+ label = "bootloader env redundant";
+ reg = <0x100000 0x40000>;
+ };
+
+ bootloaderenv@140000 {
+ label = "bootloader env";
+ reg = <0x140000 0x40000>;
+ };
+
+ dtb@180000 {
+ label = "device tree";
+ reg = <0x180000 0x80000>;
+ };
+
+ kernel@200000 {
+ label = "kernel";
+ reg = <0x200000 0x600000>;
+ };
+ };
+};
+
+&pioA {
+ pinctrl_flx1_default: flx1_usart_default {
+ pinmux = <PIN_PA24__FLEXCOM1_IO0>,
+ <PIN_PA23__FLEXCOM1_IO1>,
+ <PIN_PA25__FLEXCOM1_IO3>,
+ <PIN_PA26__FLEXCOM1_IO4>;
+ bias-disable;
+ };
+
+ pinctrl_i2c0_default: i2c0_default {
+ pinmux = <PIN_PD21__TWD0>,
+ <PIN_PD22__TWCK0>;
+ bias-disable;
+ };
+
+ pinctrl_i2c1_default: i2c1_default {
+ pinmux = <PIN_PD19__TWD1>,
+ <PIN_PD20__TWCK1>;
+ bias-disable;
+ };
+
+ pinctrl_macb0_default: macb0_default {
+ pinmux = <PIN_PB14__GTXCK>,
+ <PIN_PB15__GTXEN>,
+ <PIN_PB16__GRXDV>,
+ <PIN_PB17__GRXER>,
+ <PIN_PB18__GRX0>,
+ <PIN_PB19__GRX1>,
+ <PIN_PB20__GTX0>,
+ <PIN_PB21__GTX1>,
+ <PIN_PB22__GMDC>,
+ <PIN_PB23__GMDIO>;
+ bias-disable;
+ };
+
+ pinctrl_macb0_phy_irq: macb0_phy_irq {
+ pinmux = <PIN_PB24__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_qspi1_default: qspi1_default {
+ pinmux = <PIN_PB5__QSPI1_SCK>,
+ <PIN_PB6__QSPI1_CS>,
+ <PIN_PB7__QSPI1_IO0>,
+ <PIN_PB8__QSPI1_IO1>,
+ <PIN_PB9__QSPI1_IO2>,
+ <PIN_PB10__QSPI1_IO3>;
+ bias-pull-up;
+ };
+};
+
diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts
new file mode 100644
index 000000000000..0b9fa2942dff
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts
@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * at91-sama5d27_wlsom1_ek.dts - Device Tree file for SAMA5D27 WLSOM1 EK
+ *
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
+ */
+/dts-v1/;
+#include "at91-sama5d27_wlsom1.dtsi"
+
+/ {
+ model = "Microchip SAMA5D27 WLSOM1 EK";
+ compatible = "microchip,sama5d27-wlsom1-ek", "microchip,sama5d27-wlsom1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
+
+ aliases {
+ serial0 = &uart0; /* DBGU */
+ serial1 = &uart6; /* BT */
+ serial2 = &uart5; /* mikro BUS 2 */
+ serial3 = &uart3; /* mikro BUS 1 */
+ i2c1 = &i2c1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_key_gpio_default>;
+ status = "okay";
+
+ sw4 {
+ label = "USER BUTTON";
+ gpios = <&pioA PIN_PB2 GPIO_ACTIVE_LOW>;
+ linux,code = <0x104>;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led_gpio_default>;
+ status = "okay";
+
+ red {
+ label = "red";
+ gpios = <&pioA PIN_PA6 GPIO_ACTIVE_HIGH>;
+ };
+
+ green {
+ label = "green";
+ gpios = <&pioA PIN_PA7 GPIO_ACTIVE_HIGH>;
+ };
+
+ blue {
+ label = "blue";
+ gpios = <&pioA PIN_PA8 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&adc {
+ vddana-supply = <&vdd_3v3>;
+ vref-supply = <&vdd_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc_default>;
+ status = "okay";
+};
+
+&flx0 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+ status = "okay";
+
+ uart5: serial@200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(11))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(12))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
+ clock-names = "usart";
+ pinctrl-0 = <&pinctrl_flx0_default>;
+ pinctrl-names = "default";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "okay";
+ };
+};
+
+&flx1 {
+ status = "okay";
+
+ uart6: serial@200 {
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "okay";
+ };
+};
+
+&macb0 {
+ status = "okay";
+};
+
+&pioA {
+ /*
+ * There is no real pinmux for ADC, if the pin
+ * is not requested by another peripheral then
+ * the muxing is done when channel is enabled.
+ * Requesting pins for ADC is GPIO is
+ * encouraged to prevent conflicts and to
+ * disable bias in order to be in the same
+ * state when the pin is not muxed to the adc.
+ */
+ pinctrl_adc_default: adc_default {
+ pinmux = <PIN_PD25__GPIO>,
+ <PIN_PD26__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_flx0_default: flx0_usart_default {
+ pinmux = <PIN_PB28__FLEXCOM0_IO0>,
+ <PIN_PB29__FLEXCOM0_IO1>;
+ bias-disable;
+ };
+
+ pinctrl_key_gpio_default: key_gpio_default {
+ pinmux = <PIN_PB2__GPIO>;
+ bias-pull-up;
+ };
+
+ pinctrl_led_gpio_default: led_gpio_default {
+ pinmux = <PIN_PA6__GPIO>,
+ <PIN_PA7__GPIO>,
+ <PIN_PA8__GPIO>;
+ bias-pull-down;
+ };
+
+ pinctrl_sdmmc0_default: sdmmc0_default {
+ cmd_data {
+ pinmux = <PIN_PA1__SDMMC0_CMD>,
+ <PIN_PA2__SDMMC0_DAT0>,
+ <PIN_PA3__SDMMC0_DAT1>,
+ <PIN_PA4__SDMMC0_DAT2>,
+ <PIN_PA5__SDMMC0_DAT3>;
+ bias-disable;
+ };
+
+ ck_cd_vddsel {
+ pinmux = <PIN_PA0__SDMMC0_CK>,
+ <PIN_PA11__SDMMC0_VDDSEL>,
+ <PIN_PA12__SDMMC0_WP>,
+ <PIN_PA13__SDMMC0_CD>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_uart0_default: uart0_default {
+ pinmux = <PIN_PB26__URXD0>,
+ <PIN_PB27__UTXD0>;
+ bias-disable;
+ };
+
+ pinctrl_uart3_default: uart3_default {
+ pinmux = <PIN_PB11__URXD3>,
+ <PIN_PB12__UTXD3>;
+ bias-disable;
+ };
+
+ pinctrl_pwm0_default: pwm0_default {
+ pinmux = <PIN_PA31__PWML0>,
+ <PIN_PA30__PWMH0>;
+ bias-disable;
+ };
+
+ pinctrl_usb_default: usb_default {
+ pinmux = <PIN_PA10__GPIO>;
+ bias-disable;
+ };
+};
+
+&pwm0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default>;
+ status = "okay";
+};
+
+&qspi1 {
+ status = "okay";
+
+ qspi1_flash: spi_flash@0 {
+ status = "okay";
+ };
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ mmc-ddr-3_3v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc0_default>;
+ status = "okay";
+};
+
+&shutdown_controller {
+ atmel,shdwc-debouncer = <976>;
+ atmel,wakeup-rtc-timer;
+
+ input@0 {
+ reg = <0>;
+ atmel,wakeup-type = "low";
+ };
+};
+
+&tcb0 {
+ timer0: timer@0 {
+ compatible = "atmel,tcb-timer";
+ reg = <0>;
+ };
+
+ timer1: timer@1 {
+ compatible = "atmel,tcb-timer";
+ reg = <1>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3_default>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "okay";
+};
+
+&usb1 {
+ num-ports = <3>;
+ atmel,vbus-gpio = <0
+ &pioA PIN_PA10 GPIO_ACTIVE_HIGH
+ 0
+ >;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_default>;
+ status = "okay";
+};
+
+&usb2 {
+ phy_type = "hsic";
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
+
diff --git a/arch/arm/boot/dts/at91-smartkiz.dts b/arch/arm/boot/dts/at91-smartkiz.dts
new file mode 100644
index 000000000000..106f23ba4a3b
--- /dev/null
+++ b/arch/arm/boot/dts/at91-smartkiz.dts
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017-2018 Overkiz SAS
+ * Author: Mickael Gardet <m.gardet@overkiz.com>
+ * Kévin Raymond <k.raymond@overkiz.com>
+ * Dorian Rocipon <d.rocipon@overkiz.com>
+ */
+/dts-v1/;
+#include "at91-kizboxmini-common.dtsi"
+
+/ {
+ model = "Overkiz SmartKiz";
+ compatible = "overkiz,smartkiz", "atmel,at91sam9g25",
+ "atmel,at91sam9x5", "atmel,at91sam9";
+
+ clocks {
+ adc_op_clk {
+ status = "okay";
+ };
+ };
+
+ aliases {
+ serial5 = &uart0;
+ };
+
+ pio_keys {
+ hk_reset {
+ label = "HK_RESET";
+ gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
+ };
+
+ power_rf {
+ label = "POWER_RF";
+ gpios = <&pioA 20 GPIO_ACTIVE_HIGH>;
+ };
+
+ power_wifi {
+ label = "POWER_WIFI";
+ gpios = <&pioA 21 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&pinctrl {
+ i2c1 {
+ pinctrl_i2c1: i2c1-0 {
+ atmel,pins =
+ <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
+ AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;
+ };
+ };
+
+ adc0 {
+ pinctrl_adc0_ad0: adc0_ad0-0 {
+ /* pull-up disable */
+ atmel,pins = <AT91_PIOB 11 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ pinctrl_adc0_ad5: adc0_ad5-0 {
+ /* pull-up disable */
+ atmel,pins = <AT91_PIOB 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ pinctrl_adc0_ad6: adc0_ad6-0 {
+ /* pull-up disable */
+ atmel,pins = <AT91_PIOB 17 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ pinctrl_adc0_ad11: adc0_ad11-0 {
+ /* pull-up disable */
+ atmel,pins = <AT91_PIOB 10 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ };
+};
+
+&i2c1 {
+ dmas = <0>, <0>;
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "disabled";
+};
+
+&macb0 {
+ status = "disabled";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&leds {
+ blue {
+ status = "okay";
+ };
+};
+
+&adc0 {
+ atmel,adc-vref = <2500>;
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &pinctrl_adc0_ad0
+ &pinctrl_adc0_ad5
+ &pinctrl_adc0_ad6
+ &pinctrl_adc0_ad11
+ >;
+ atmel,adc-channels-used = <0x0861>;
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index dee9c0c8a096..6afbb48e7ff0 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -187,7 +187,7 @@
usart0 {
pinctrl_usart0: usart0-0 {
atmel,pins =
- <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE
+ <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@@ -221,7 +221,7 @@
usart1 {
pinctrl_usart1: usart1-0 {
atmel,pins =
- <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE
+ <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@@ -239,7 +239,7 @@
usart2 {
pinctrl_usart2: usart2-0 {
atmel,pins =
- <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE
+ <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@@ -257,7 +257,7 @@
usart3 {
pinctrl_usart3: usart3-0 {
atmel,pins =
- <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE
+ <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@@ -275,7 +275,7 @@
uart0 {
pinctrl_uart0: uart0-0 {
atmel,pins =
- <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE
+ <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP
AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
};
};
@@ -283,7 +283,7 @@
uart1 {
pinctrl_uart1: uart1-0 {
atmel,pins =
- <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE
+ <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
};
@@ -738,7 +738,7 @@
status = "disabled";
};
- watchdog@fffffd40 {
+ watchdog: watchdog@fffffd40 {
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
@@ -793,7 +793,7 @@
};
};
- i2c-gpio-0 {
+ i2c_gpio0: i2c-gpio-0 {
compatible = "i2c-gpio";
gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */
&pioA 24 GPIO_ACTIVE_HIGH /* scl */
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index dba025a98527..5ed3d745ac86 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -329,7 +329,7 @@
usart0 {
pinctrl_usart0: usart0-0 {
atmel,pins =
- <AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
<AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@@ -347,7 +347,7 @@
usart1 {
pinctrl_usart1: usart1-0 {
atmel,pins =
- <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
<AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@@ -365,7 +365,7 @@
usart2 {
pinctrl_usart2: usart2-0 {
atmel,pins =
- <AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
<AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 99678abdda93..5c990cfae254 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -183,7 +183,7 @@
usart0 {
pinctrl_usart0: usart0-0 {
atmel,pins =
- <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE
+ <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@@ -201,7 +201,7 @@
usart1 {
pinctrl_usart1: usart1-0 {
atmel,pins =
- <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE
+ <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@@ -219,7 +219,7 @@
usart2 {
pinctrl_usart2: usart2-0 {
atmel,pins =
- <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE
+ <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 691c95ea6175..fd179097a4bf 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -556,7 +556,7 @@
usart0 {
pinctrl_usart0: usart0-0 {
atmel,pins =
- <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE
+ <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@@ -574,7 +574,7 @@
usart1 {
pinctrl_usart1: usart1-0 {
atmel,pins =
- <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE
+ <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@@ -592,7 +592,7 @@
usart2 {
pinctrl_usart2: usart2-0 {
atmel,pins =
- <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE
+ <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@@ -610,7 +610,7 @@
usart3 {
pinctrl_usart3: usart3-0 {
atmel,pins =
- <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE
+ <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
index 8643b7151565..ea024e4b6e09 100644
--- a/arch/arm/boot/dts/at91sam9rl.dtsi
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -682,7 +682,7 @@
usart0 {
pinctrl_usart0: usart0-0 {
atmel,pins =
- <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
<AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@@ -721,7 +721,7 @@
usart1 {
pinctrl_usart1: usart1-0 {
atmel,pins =
- <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
<AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@@ -744,7 +744,7 @@
usart2 {
pinctrl_usart2: usart2-0 {
atmel,pins =
- <AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
<AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@@ -767,7 +767,7 @@
usart3 {
pinctrl_usart3: usart3-0 {
atmel,pins =
- <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+ <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
<AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
index 8eedd6eb409b..d1e684d0acfd 100644
--- a/arch/arm/boot/dts/bcm2711.dtsi
+++ b/arch/arm/boot/dts/bcm2711.dtsi
@@ -12,26 +12,6 @@
interrupt-parent = <&gicv2>;
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
-
- /*
- * arm64 reserves the CMA by default somewhere in ZONE_DMA32,
- * that's not good enough for the BCM2711 as some devices can
- * only address the lower 1G of memory (ZONE_DMA).
- */
- linux,cma {
- compatible = "shared-dma-pool";
- size = <0x2000000>; /* 32MB */
- alloc-ranges = <0x0 0x00000000 0x40000000>;
- reusable;
- linux,cma-default;
- };
- };
-
-
soc {
/*
* Defined ranges:
@@ -123,10 +103,8 @@
};
rng@7e104000 {
- interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
-
- /* RNG is incompatible with brcm,bcm2835-rng */
- status = "disabled";
+ compatible = "brcm,bcm2711-rng200";
+ reg = <0x7e104000 0x28>;
};
uart2: serial@7e201400 {
@@ -342,7 +320,36 @@
#address-cells = <2>;
#size-cells = <1>;
- ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>;
+ ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>,
+ <0x6 0x00000000 0x6 0x00000000 0x40000000>;
+
+ pcie0: pcie@7d500000 {
+ compatible = "brcm,bcm2711-pcie";
+ reg = <0x0 0x7d500000 0x9310>;
+ device_type = "pci";
+ #address-cells = <3>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pcie", "msi";
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
+ IRQ_TYPE_LEVEL_HIGH>;
+ msi-controller;
+ msi-parent = <&pcie0>;
+
+ ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
+ 0x0 0x04000000>;
+ /*
+ * The wrapper around the PCIe block has a bug
+ * preventing it from accessing beyond the first 3GB of
+ * memory.
+ */
+ dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
+ 0x0 0xc0000000>;
+ brcm,enable-ssc;
+ };
genet: ethernet@7d580000 {
compatible = "brcm,bcm2711-genet-v5";
@@ -840,6 +847,19 @@
};
};
+&rmem {
+ #address-cells = <2>;
+};
+
+&cma {
+ /*
+ * arm64 reserves the CMA by default somewhere in ZONE_DMA32,
+ * that's not good enough for the BCM2711 as some devices can
+ * only address the lower 1G of memory (ZONE_DMA).
+ */
+ alloc-ranges = <0x0 0x00000000 0x40000000>;
+};
+
&i2c0 {
compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/bcm2835-common.dtsi b/arch/arm/boot/dts/bcm2835-common.dtsi
index fe1ab40c7f22..2b1d9d4c0cde 100644
--- a/arch/arm/boot/dts/bcm2835-common.dtsi
+++ b/arch/arm/boot/dts/bcm2835-common.dtsi
@@ -70,6 +70,12 @@
system-power-controller;
};
+ rng@7e104000 {
+ compatible = "brcm,bcm2835-rng";
+ reg = <0x7e104000 0x10>;
+ interrupts = <2 29>;
+ };
+
pixelvalve@7e206000 {
compatible = "brcm,bcm2835-pixelvalve0";
reg = <0x7e206000 0x100>;
diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
index 839491628e87..e1abe8c730ce 100644
--- a/arch/arm/boot/dts/bcm283x.dtsi
+++ b/arch/arm/boot/dts/bcm283x.dtsi
@@ -30,6 +30,19 @@
stdout-path = "serial0:115200n8";
};
+ rmem: reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ size = <0x4000000>; /* 64MB */
+ reusable;
+ linux,cma-default;
+ };
+ };
+
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <0>;
@@ -84,12 +97,6 @@
<&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
};
- rng@7e104000 {
- compatible = "brcm,bcm2835-rng";
- reg = <0x7e104000 0x10>;
- interrupts = <2 29>;
- };
-
mailbox: mailbox@7e00b880 {
compatible = "brcm,bcm2835-mbox";
reg = <0x7e00b880 0x40>;
diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts
index a2c9de35ddfb..536fb24f38bb 100644
--- a/arch/arm/boot/dts/bcm958625hr.dts
+++ b/arch/arm/boot/dts/bcm958625hr.dts
@@ -55,18 +55,9 @@
priority = <200>;
};
- /* Hardware I2C block cannot do more than 63 bytes per transfer,
- * which would prevent reading from a SFP's EEPROM (256 byte).
- */
- i2c1: i2c {
- compatible = "i2c-gpio";
- sda-gpios = <&gpioa 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpioa 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- };
-
sfp: sfp {
compatible = "sff,sfp";
- i2c-bus = <&i2c1>;
+ i2c-bus = <&i2c0>;
mod-def0-gpios = <&gpioa 28 GPIO_ACTIVE_LOW>;
los-gpios = <&gpioa 24 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&gpioa 30 GPIO_ACTIVE_HIGH>;
@@ -74,6 +65,10 @@
};
};
+&i2c0 {
+ status = "okay";
+};
+
&amac0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/dm3725.dtsi b/arch/arm/boot/dts/dm3725.dtsi
new file mode 100644
index 000000000000..d24e906a14b1
--- /dev/null
+++ b/arch/arm/boot/dts/dm3725.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020 André Hentschel <nerv@dawncrow.de>
+ */
+
+#include "omap36xx.dtsi"
+
+&sgx_module {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi
index 7e7aa101d8a4..c1740868042a 100644
--- a/arch/arm/boot/dts/dra7-l4.dtsi
+++ b/arch/arm/boot/dts/dra7-l4.dtsi
@@ -186,7 +186,6 @@
target-module@56000 { /* 0x4a056000, ap 9 02.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "dma_system";
reg = <0x56000 0x4>,
<0x5602c 0x4>,
<0x56028 0x4>;
@@ -212,7 +211,7 @@
ranges = <0x0 0x56000 0x1000>;
sdma: dma-controller@0 {
- compatible = "ti,omap4430-sdma";
+ compatible = "ti,omap4430-sdma", "ti,omap-sdma";
reg = <0x0 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
@@ -234,7 +233,6 @@
target-module@80000 { /* 0x4a080000, ap 13 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "ocp2scp1";
reg = <0x80000 0x4>,
<0x80010 0x4>,
<0x80014 0x4>;
@@ -302,7 +300,6 @@
target-module@90000 { /* 0x4a090000, ap 59 42.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "ocp2scp3";
reg = <0x90000 0x4>,
<0x90010 0x4>,
<0x90014 0x4>;
@@ -394,7 +391,6 @@
target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */
compatible = "ti,sysc-omap4-sr", "ti,sysc";
- ti,hwmods = "smartreflex_mpu";
reg = <0xd9038 0x4>;
reg-names = "sysc";
ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
@@ -414,7 +410,6 @@
target-module@dd000 { /* 0x4a0dd000, ap 19 18.0 */
compatible = "ti,sysc-omap4-sr", "ti,sysc";
- ti,hwmods = "smartreflex_core";
reg = <0xdd038 0x4>;
reg-names = "sysc";
ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
@@ -471,7 +466,6 @@
target-module@f6000 { /* 0x4a0f6000, ap 25 78.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "spinlock";
reg = <0xf6000 0x4>,
<0xf6010 0x4>,
<0xf6014 0x4>;
@@ -1233,7 +1227,6 @@
target-module@3e000 { /* 0x4803e000, ap 11 56.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer9";
reg = <0x3e000 0x4>,
<0x3e010 0x4>;
reg-names = "rev", "sysc";
@@ -1748,7 +1741,6 @@
target-module@78000 { /* 0x48078000, ap 39 0a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "elm";
reg = <0x78000 0x4>,
<0x78010 0x4>,
<0x78014 0x4>;
@@ -1842,7 +1834,6 @@
target-module@86000 { /* 0x48086000, ap 41 5e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer10";
reg = <0x86000 0x4>,
<0x86010 0x4>;
reg-names = "rev", "sysc";
@@ -1870,7 +1861,6 @@
target-module@88000 { /* 0x48088000, ap 43 66.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer11";
reg = <0x88000 0x4>,
<0x88010 0x4>;
reg-names = "rev", "sysc";
@@ -2044,6 +2034,37 @@
<0x00001000 0x000a5000 0x00001000>;
};
+ des_target: target-module@a5000 { /* 0x480a5000 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0xa5030 0x4>,
+ <0xa5034 0x4>,
+ <0xa5038 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
+ clocks = <&l4sec_clkctrl DRA7_L4SEC_DES_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xa5000 0x00001000>;
+
+ des: des@0 {
+ compatible = "ti,omap4-des";
+ reg = <0 0xa0>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
+ dma-names = "tx", "rx";
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
+ };
+ };
+
target-module@a8000 { /* 0x480a8000, ap 59 1a.0 */
compatible = "ti,sysc";
status = "disabled";
@@ -2490,7 +2511,6 @@
target-module@3e000 { /* 0x4843e000, ap 25 30.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "epwmss0";
reg = <0x3e000 0x4>,
<0x3e004 0x4>;
reg-names = "rev", "sysc";
@@ -2537,7 +2557,6 @@
target-module@40000 { /* 0x48440000, ap 27 38.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "epwmss1";
reg = <0x40000 0x4>,
<0x40004 0x4>;
reg-names = "rev", "sysc";
@@ -2584,7 +2603,6 @@
target-module@42000 { /* 0x48442000, ap 29 20.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "epwmss2";
reg = <0x42000 0x4>,
<0x42004 0x4>;
reg-names = "rev", "sysc";
@@ -3326,7 +3344,6 @@
target-module@20000 { /* 0x48820000, ap 5 08.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer5";
reg = <0x20000 0x4>,
<0x20010 0x4>;
reg-names = "rev", "sysc";
@@ -3354,7 +3371,6 @@
target-module@22000 { /* 0x48822000, ap 7 24.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer6";
reg = <0x22000 0x4>,
<0x22010 0x4>;
reg-names = "rev", "sysc";
@@ -3382,7 +3398,6 @@
target-module@24000 { /* 0x48824000, ap 9 26.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer7";
reg = <0x24000 0x4>,
<0x24010 0x4>;
reg-names = "rev", "sysc";
@@ -3410,7 +3425,6 @@
target-module@26000 { /* 0x48826000, ap 11 0c.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer8";
reg = <0x26000 0x4>,
<0x26010 0x4>;
reg-names = "rev", "sysc";
@@ -3438,7 +3452,6 @@
target-module@28000 { /* 0x48828000, ap 13 16.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer13";
reg = <0x28000 0x4>,
<0x28010 0x4>;
reg-names = "rev", "sysc";
@@ -3466,7 +3479,6 @@
target-module@2a000 { /* 0x4882a000, ap 15 10.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer14";
reg = <0x2a000 0x4>,
<0x2a010 0x4>;
reg-names = "rev", "sysc";
@@ -3494,7 +3506,6 @@
target-module@2c000 { /* 0x4882c000, ap 17 02.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer15";
reg = <0x2c000 0x4>,
<0x2c010 0x4>;
reg-names = "rev", "sysc";
@@ -3522,7 +3533,6 @@
target-module@2e000 { /* 0x4882e000, ap 19 14.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer16";
reg = <0x2e000 0x4>,
<0x2e010 0x4>;
reg-names = "rev", "sysc";
@@ -4422,7 +4432,6 @@
target-module@0 { /* 0x4ae20000, ap 19 08.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer12";
reg = <0x0 0x4>,
<0x10 0x4>;
reg-names = "rev", "sysc";
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 73e5011f531a..40ac514702ac 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -377,44 +377,120 @@
ti,hwmods = "dmm";
};
- mmu0_dsp1: mmu@40d01000 {
- compatible = "ti,dra7-dsp-iommu";
- reg = <0x40d01000 0x100>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu0_dsp1";
- #iommu-cells = <0>;
- ti,syscon-mmuconfig = <&dsp1_system 0x0>;
- status = "disabled";
+ target-module@40d01000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x40d01000 0x4>,
+ <0x40d01010 0x4>,
+ <0x40d01014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_dsp1 1>;
+ reset-names = "rstctrl";
+ ranges = <0x0 0x40d01000 0x1000>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+
+ mmu0_dsp1: mmu@0 {
+ compatible = "ti,dra7-dsp-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,syscon-mmuconfig = <&dsp1_system 0x0>;
+ };
};
- mmu1_dsp1: mmu@40d02000 {
- compatible = "ti,dra7-dsp-iommu";
- reg = <0x40d02000 0x100>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu1_dsp1";
- #iommu-cells = <0>;
- ti,syscon-mmuconfig = <&dsp1_system 0x1>;
- status = "disabled";
+ target-module@40d02000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x40d02000 0x4>,
+ <0x40d02010 0x4>,
+ <0x40d02014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_dsp1 1>;
+ reset-names = "rstctrl";
+ ranges = <0x0 0x40d02000 0x1000>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+
+ mmu1_dsp1: mmu@0 {
+ compatible = "ti,dra7-dsp-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,syscon-mmuconfig = <&dsp1_system 0x1>;
+ };
};
- mmu_ipu1: mmu@58882000 {
- compatible = "ti,dra7-iommu";
- reg = <0x58882000 0x100>;
- interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu_ipu1";
- #iommu-cells = <0>;
- ti,iommu-bus-err-back;
- status = "disabled";
+ target-module@58882000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x58882000 0x4>,
+ <0x58882010 0x4>,
+ <0x58882014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_ipu 2>;
+ reset-names = "rstctrl";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x58882000 0x100>;
+
+ mmu_ipu1: mmu@0 {
+ compatible = "ti,dra7-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,iommu-bus-err-back;
+ };
};
- mmu_ipu2: mmu@55082000 {
- compatible = "ti,dra7-iommu";
- reg = <0x55082000 0x100>;
- interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu_ipu2";
- #iommu-cells = <0>;
- ti,iommu-bus-err-back;
- status = "disabled";
+ target-module@55082000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x55082000 0x4>,
+ <0x55082010 0x4>,
+ <0x55082014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_core 2>;
+ reset-names = "rstctrl";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x55082000 0x100>;
+
+ mmu_ipu2: mmu@0 {
+ compatible = "ti,dra7-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,iommu-bus-err-back;
+ };
};
abb_mpu: regulator-abb-mpu {
@@ -652,48 +728,96 @@
};
};
- aes1: aes@4b500000 {
- compatible = "ti,omap4-aes";
- ti,hwmods = "aes1";
- reg = <0x4b500000 0xa0>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
- dma-names = "tx", "rx";
- clocks = <&l3_iclk_div>;
- clock-names = "fck";
- };
-
- aes2: aes@4b700000 {
- compatible = "ti,omap4-aes";
- ti,hwmods = "aes2";
- reg = <0x4b700000 0xa0>;
- interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
- dma-names = "tx", "rx";
- clocks = <&l3_iclk_div>;
+ aes1_target: target-module@4b500000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x4b500080 0x4>,
+ <0x4b500084 0x4>,
+ <0x4b500088 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4sec_clkdm */
+ clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>;
clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4b500000 0x1000>;
+
+ aes1: aes@0 {
+ compatible = "ti,omap4-aes";
+ reg = <0 0xa0>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
+ dma-names = "tx", "rx";
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
+ };
};
- des: des@480a5000 {
- compatible = "ti,omap4-des";
- ti,hwmods = "des";
- reg = <0x480a5000 0xa0>;
- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
- dma-names = "tx", "rx";
- clocks = <&l3_iclk_div>;
+ aes2_target: target-module@4b700000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x4b700080 0x4>,
+ <0x4b700084 0x4>,
+ <0x4b700088 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4sec_clkdm */
+ clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>;
clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4b700000 0x1000>;
+
+ aes2: aes@0 {
+ compatible = "ti,omap4-aes";
+ reg = <0 0xa0>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
+ dma-names = "tx", "rx";
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
+ };
};
- sham: sham@53100000 {
- compatible = "ti,omap5-sham";
- ti,hwmods = "sham";
- reg = <0x4b101000 0x300>;
- interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&edma_xbar 119 0>;
- dma-names = "rx";
- clocks = <&l3_iclk_div>;
+ sham_target: target-module@4b101000 {
+ compatible = "ti,sysc-omap3-sham", "ti,sysc";
+ reg = <0x4b101100 0x4>,
+ <0x4b101110 0x4>,
+ <0x4b101114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
+ clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>;
clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4b101000 0x1000>;
+
+ sham: sham@0 {
+ compatible = "ti,omap5-sham";
+ reg = <0 0x300>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&edma_xbar 119 0>;
+ dma-names = "rx";
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
+ };
};
opp_supply_mpu: opp-supply@4a003b20 {
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index d1b5b76bc5a8..c5abc436ca1f 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -66,24 +66,63 @@
};
};
- mmu0_dsp2: mmu@41501000 {
- compatible = "ti,dra7-dsp-iommu";
- reg = <0x41501000 0x100>;
- interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu0_dsp2";
- #iommu-cells = <0>;
- ti,syscon-mmuconfig = <&dsp2_system 0x0>;
- status = "disabled";
+ target-module@41501000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x41501000 0x4>,
+ <0x41501010 0x4>,
+ <0x41501014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_dsp2 1>;
+ reset-names = "rstctrl";
+ ranges = <0x0 0x41501000 0x1000>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+
+ mmu0_dsp2: mmu@0 {
+ compatible = "ti,dra7-dsp-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,syscon-mmuconfig = <&dsp2_system 0x0>;
+ };
};
- mmu1_dsp2: mmu@41502000 {
- compatible = "ti,dra7-dsp-iommu";
- reg = <0x41502000 0x100>;
- interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu1_dsp2";
- #iommu-cells = <0>;
- ti,syscon-mmuconfig = <&dsp2_system 0x1>;
- status = "disabled";
+ target-module@41502000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x41502000 0x4>,
+ <0x41502010 0x4>,
+ <0x41502014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+
+ clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_dsp2 1>;
+ reset-names = "rstctrl";
+ ranges = <0x0 0x41502000 0x1000>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+
+ mmu1_dsp2: mmu@0 {
+ compatible = "ti,dra7-dsp-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,syscon-mmuconfig = <&dsp2_system 0x1>;
+ };
};
};
};
diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts
index 1fb6f13fb5e2..86a3e79909a8 100644
--- a/arch/arm/boot/dts/dra76-evm.dts
+++ b/arch/arm/boot/dts/dra76-evm.dts
@@ -13,6 +13,13 @@
model = "TI DRA762 EVM";
compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7";
+ aliases {
+ display0 = &hdmi0;
+
+ sound0 = &sound0;
+ sound1 = &hdmi;
+ };
+
memory@0 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
@@ -116,6 +123,48 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
+
+ hdmi0: connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&tpd12s015_out>;
+ };
+ };
+ };
+
+ tpd12s015: encoder {
+ compatible = "ti,tpd12s015";
+
+ gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>, /* gpio7_30, CT CP HPD */
+ <&gpio7 31 GPIO_ACTIVE_HIGH>, /* gpio7_31, LS OE */
+ <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpd12s015_in: endpoint {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpd12s015_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
};
&i2c1 {
@@ -411,6 +460,23 @@
phy-supply = <&ldo3_reg>;
};
+&dss {
+ status = "ok";
+ vdda_video-supply = <&ldo5_reg>;
+};
+
+&hdmi {
+ status = "ok";
+
+ vdda-supply = <&ldo1_reg>;
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&tpd12s015_in>;
+ };
+ };
+};
+
&qspi {
spi-max-frequency = <96000000>;
m25p80@0 {
diff --git a/arch/arm/boot/dts/e60k02.dtsi b/arch/arm/boot/dts/e60k02.dtsi
index 5a2c5320437d..ce50c4dc6f2a 100644
--- a/arch/arm/boot/dts/e60k02.dtsi
+++ b/arch/arm/boot/dts/e60k02.dtsi
@@ -48,7 +48,8 @@
};
};
- memory {
+ memory@80000000 {
+ device_type = "memory";
reg = <0x80000000 0x20000000>;
};
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index b016b0b68306..044e5da64a76 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -145,12 +145,12 @@
#size-cells = <1>;
ranges = <0 0x02020000 0x40000>;
- smp-sysram@0 {
+ smp-sram@0 {
compatible = "samsung,exynos4210-sysram";
reg = <0x0 0x1000>;
};
- smp-sysram@3f000 {
+ smp-sram@3f000 {
compatible = "samsung,exynos4210-sysram-ns";
reg = <0x3f000 0x1000>;
};
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 09d3d54d09ff..a1bdf7830a87 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -590,16 +590,16 @@
};
&sysram {
- smp-sysram@0 {
+ smp-sram@0 {
status = "disabled";
};
- smp-sysram@5000 {
+ smp-sram@5000 {
compatible = "samsung,exynos4210-sysram";
reg = <0x5000 0x1000>;
};
- smp-sysram@1f000 {
+ smp-sram@1f000 {
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 554819ae1446..b4466232f0c1 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -79,12 +79,12 @@
#size-cells = <1>;
ranges = <0 0x02020000 0x20000>;
- smp-sysram@0 {
+ smp-sram@0 {
compatible = "samsung,exynos4210-sysram";
reg = <0x0 0x1000>;
};
- smp-sysram@1f000 {
+ smp-sram@1f000 {
compatible = "samsung,exynos4210-sysram-ns";
reg = <0x1f000 0x1000>;
};
diff --git a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi
index ce87d2ff27aa..31719c079d67 100644
--- a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi
+++ b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi
@@ -168,3 +168,8 @@
vdda-supply = <&ldo17_reg>;
status = "okay";
};
+
+&touchkey_reg {
+ gpio = <&gpm0 0 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi
index 83be3a797411..3023bc3b68ce 100644
--- a/arch/arm/boot/dts/exynos4412-midas.dtsi
+++ b/arch/arm/boot/dts/exynos4412-midas.dtsi
@@ -13,6 +13,7 @@
#include "exynos4412.dtsi"
#include "exynos4412-ppmu-common.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/maxim,max77686.h>
#include <dt-bindings/pinctrl/samsung.h>
@@ -92,6 +93,15 @@
enable-active-high;
};
+ touchkey_reg: voltage-regulator-6 {
+ compatible = "regulator-fixed";
+ regulator-name = "LED_VDD_3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ status = "disabled";
+ };
+
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@@ -197,6 +207,25 @@
};
};
+ i2c-gpio-4 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpl0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpl0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchkey@20 {
+ compatible = "cypress,midas-touchkey";
+ reg = <0x20>;
+ vdd-supply = <&touchkey_reg>;
+ vcc-supply = <&ldo5_reg>;
+ interrupt-parent = <&gpj0>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ linux,keycodes = <KEY_BACK KEY_MENU>;
+ };
+ };
+
i2c-mhl {
compatible = "i2c-gpio";
gpios = <&gpf0 4 GPIO_ACTIVE_HIGH>, <&gpf0 6 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/exynos4412-n710x.dts b/arch/arm/boot/dts/exynos4412-n710x.dts
index fe2bfd76cc4e..98cd1284cd90 100644
--- a/arch/arm/boot/dts/exynos4412-n710x.dts
+++ b/arch/arm/boot/dts/exynos4412-n710x.dts
@@ -73,3 +73,8 @@
vdda-supply = <&cam_vdda_reg>;
status = "okay";
};
+
+&touchkey_reg {
+ gpio = <&gpm0 5 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index ea55f377d17c..9c39e82e4ecb 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -267,7 +267,7 @@
intn-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>;
connect-gpios = <&gpx3 4 GPIO_ACTIVE_HIGH>;
- reset-gpios = <&gpx3 5 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
initial-mode = <1>;
};
diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/exynos4412-tiny4412.dts
index 01f37b5ac9c4..3a91de8a8082 100644
--- a/arch/arm/boot/dts/exynos4412-tiny4412.dts
+++ b/arch/arm/boot/dts/exynos4412-tiny4412.dts
@@ -66,6 +66,31 @@
clock-frequency = <24000000>;
};
};
+
+ panel {
+ compatible = "innolux,at070tn92";
+
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&lcdc_output>;
+ };
+ };
+ };
+};
+
+&fimd {
+ pinctrl-0 = <&lcd_clk>, <&lcd_data24>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ port@3 {
+ reg = <3>;
+ lcdc_output: endpoint {
+ remote-endpoint = <&panel_input>;
+ };
+ };
};
&rtc {
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 5022aa574b26..48868947373e 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -195,12 +195,12 @@
#size-cells = <1>;
ranges = <0 0x02020000 0x40000>;
- smp-sysram@0 {
+ smp-sram@0 {
compatible = "samsung,exynos4210-sysram";
reg = <0x0 0x1000>;
};
- smp-sysram@2f000 {
+ smp-sram@2f000 {
compatible = "samsung,exynos4210-sysram-ns";
reg = <0x2f000 0x1000>;
};
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 4801ca759feb..22eb951c614c 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -36,7 +36,7 @@
ranges;
chipid: chipid@10000000 {
- compatible = "samsung,exynos4210-chipid", "syscon";
+ compatible = "samsung,exynos4210-chipid";
reg = <0x10000000 0x100>;
};
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index d6c85efdb465..f8ebc620f42d 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -15,7 +15,7 @@
#include "exynos5250.dtsi"
/ {
- model = "Insignal Arndale evaluation board based on EXYNOS5250";
+ model = "Insignal Arndale evaluation board based on Exynos5250";
compatible = "insignal,arndale", "samsung,exynos5250", "samsung,exynos5";
memory@40000000 {
@@ -154,7 +154,7 @@
compatible = "smsc,usb3503a";
reset-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
- connect-gpios = <&gpd1 7 GPIO_ACTIVE_LOW>;
+ connect-gpios = <&gpd1 7 GPIO_ACTIVE_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 6dc96948a9cc..5c42df024adf 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * SAMSUNG SMDK5250 board device tree source
+ * Samsung SMDK5250 board device tree source
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
@@ -12,7 +12,7 @@
#include "exynos5250.dtsi"
/ {
- model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
+ model = "Samsung SMDK5250 board based on Exynos5250";
compatible = "samsung,smdk5250", "samsung,exynos5250", "samsung,exynos5";
aliases {
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index e1f0215e3985..b6135af7ef39 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -1,16 +1,16 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * SAMSUNG EXYNOS5250 SoC device tree source
+ * Samsung Exynos5250 SoC device tree source
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
- * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
- * EXYNOS5250 based board files can include this file and provide
+ * Samsung Exynos5250 SoC device nodes are listed in this file.
+ * Exynos5250 based board files can include this file and provide
* values for board specfic bindings.
*
* Note: This file does not include device nodes for all the controllers in
- * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
+ * Exynos5250 SoC. As device tree coverage for Exynos5250 increases,
* additional nodes can be added to this file.
*/
@@ -171,12 +171,12 @@
#size-cells = <1>;
ranges = <0 0x02020000 0x30000>;
- smp-sysram@0 {
+ smp-sram@0 {
compatible = "samsung,exynos4210-sysram";
reg = <0x0 0x1000>;
};
- smp-sysram@2f000 {
+ smp-sram@2f000 {
compatible = "samsung,exynos4210-sysram-ns";
reg = <0x2f000 0x1000>;
};
diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts
index 36a2b77eeb9d..0dc2ec16aa0a 100644
--- a/arch/arm/boot/dts/exynos5260-xyref5260.dts
+++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * SAMSUNG XYREF5260 board device tree source
+ * Samsung XYREF5260 board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
@@ -10,7 +10,7 @@
#include "exynos5260.dtsi"
/ {
- model = "SAMSUNG XYREF5260 board based on EXYNOS5260";
+ model = "Samsung XYREF5260 board based on Exynos5260";
compatible = "samsung,xyref5260", "samsung,exynos5260", "samsung,exynos5";
memory@20000000 {
diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
index b0811dbbb362..154df70128f3 100644
--- a/arch/arm/boot/dts/exynos5260.dtsi
+++ b/arch/arm/boot/dts/exynos5260.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * SAMSUNG EXYNOS5260 SoC device tree source
+ * Samsung Exynos5260 SoC device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts
index e0db251e253f..4f9297ae0763 100644
--- a/arch/arm/boot/dts/exynos5410-odroidxu.dts
+++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts
@@ -170,7 +170,7 @@
intn-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
connect-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
- reset-gpios = <&gpx1 4 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpx1 4 GPIO_ACTIVE_LOW>;
initial-mode = <1>;
clock-names = "refclk";
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts
index dffa5e3ed90c..5282b5deca86 100644
--- a/arch/arm/boot/dts/exynos5410-smdk5410.dts
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * SAMSUNG SMDK5410 board device tree source
+ * Samsung SMDK5410 board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
@@ -10,7 +10,7 @@
#include "exynos5410.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ {
- model = "Samsung SMDK5410 board based on EXYNOS5410";
+ model = "Samsung SMDK5410 board based on Exynos5410";
compatible = "samsung,smdk5410", "samsung,exynos5410", "samsung,exynos5";
memory@40000000 {
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index a4b03d4c3de5..2eab80bf5f3a 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -1,12 +1,12 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * SAMSUNG EXYNOS5410 SoC device tree source
+ * Samsung Exynos5410 SoC device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
- * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
- * EXYNOS5410 based board files can include this file and provide
+ * Samsung Exynos5410 SoC device nodes are listed in this file.
+ * Exynos5410 based board files can include this file and provide
* values for board specfic bindings.
*/
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index 592d7b45ecc8..ee28d30f5476 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -15,7 +15,7 @@
#include <dt-bindings/clock/samsung,s2mps11.h>
/ {
- model = "Insignal Arndale Octa evaluation board based on EXYNOS5420";
+ model = "Insignal Arndale Octa evaluation board based on Exynos5420";
compatible = "insignal,arndale-octa", "samsung,exynos5420", "samsung,exynos5";
memory@20000000 {
diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi
index 0ee6e92a3c29..58d1c54cf925 100644
--- a/arch/arm/boot/dts/exynos5420-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * SAMSUNG EXYNOS5420 SoC cpu device tree source
+ * Samsung Exynos5420 SoC cpu device tree source
*
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 8240e5186972..e3f2afe8359a 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * SAMSUNG SMDK5420 board device tree source
+ * Samsung SMDK5420 board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
@@ -12,7 +12,7 @@
#include <dt-bindings/gpio/gpio.h>
/ {
- model = "Samsung SMDK5420 board based on EXYNOS5420";
+ model = "Samsung SMDK5420 board based on Exynos5420";
compatible = "samsung,smdk5420", "samsung,exynos5420", "samsung,exynos5";
memory@20000000 {
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index d39907a41f78..b672080e7469 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1,12 +1,12 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * SAMSUNG EXYNOS5420 SoC device tree source
+ * Samsung Exynos5420 SoC device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
- * SAMSUNG EXYNOS5420 SoC device nodes are listed in this file.
- * EXYNOS5420 based board files can include this file and provide
+ * Samsung Exynos5420 SoC device nodes are listed in this file.
+ * Exynos5420 based board files can include this file and provide
* values for board specfic bindings.
*/
@@ -48,62 +48,62 @@
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <1250000>;
+ opp-microvolt = <1250000 1250000 1500000>;
clock-latency-ns = <140000>;
};
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
- opp-microvolt = <1212500>;
+ opp-microvolt = <1212500 1212500 1500000>;
clock-latency-ns = <140000>;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
- opp-microvolt = <1175000>;
+ opp-microvolt = <1175000 1175000 1500000>;
clock-latency-ns = <140000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
- opp-microvolt = <1137500>;
+ opp-microvolt = <1137500 1137500 1500000>;
clock-latency-ns = <140000>;
};
opp-1400000000 {
opp-hz = /bits/ 64 <1400000000>;
- opp-microvolt = <1112500>;
+ opp-microvolt = <1112500 1112500 1500000>;
clock-latency-ns = <140000>;
};
opp-1300000000 {
opp-hz = /bits/ 64 <1300000000>;
- opp-microvolt = <1062500>;
+ opp-microvolt = <1062500 1062500 1500000>;
clock-latency-ns = <140000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <1037500>;
+ opp-microvolt = <1037500 1037500 1500000>;
clock-latency-ns = <140000>;
};
opp-1100000000 {
opp-hz = /bits/ 64 <1100000000>;
- opp-microvolt = <1012500>;
+ opp-microvolt = <1012500 1012500 1500000>;
clock-latency-ns = <140000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = < 987500>;
+ opp-microvolt = < 987500 987500 1500000>;
clock-latency-ns = <140000>;
};
opp-900000000 {
opp-hz = /bits/ 64 <900000000>;
- opp-microvolt = < 962500>;
+ opp-microvolt = < 962500 962500 1500000>;
clock-latency-ns = <140000>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = < 937500>;
+ opp-microvolt = < 937500 937500 1500000>;
clock-latency-ns = <140000>;
};
opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
- opp-microvolt = < 912500>;
+ opp-microvolt = < 912500 912500 1500000>;
clock-latency-ns = <140000>;
};
};
@@ -744,6 +744,56 @@
iommus = <&sysmmu_gscl1>;
};
+ gpu: gpu@11800000 {
+ compatible = "samsung,exynos5420-mali", "arm,mali-t628";
+ reg = <0x11800000 0x5000>;
+ interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "job", "mmu", "gpu";
+
+ clocks = <&clock CLK_G3D>;
+ clock-names = "core";
+ power-domains = <&g3d_pd>;
+ operating-points-v2 = <&gpu_opp_table>;
+
+ status = "disabled";
+ #cooling-cells = <2>;
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-177000000 {
+ opp-hz = /bits/ 64 <177000000>;
+ opp-microvolt = <812500>;
+ };
+ opp-266000000 {
+ opp-hz = /bits/ 64 <266000000>;
+ opp-microvolt = <862500>;
+ };
+ opp-350000000 {
+ opp-hz = /bits/ 64 <350000000>;
+ opp-microvolt = <912500>;
+ };
+ opp-420000000 {
+ opp-hz = /bits/ 64 <420000000>;
+ opp-microvolt = <962500>;
+ };
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp-543000000 {
+ opp-hz = /bits/ 64 <543000000>;
+ opp-microvolt = <1037500>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1150000>;
+ };
+ };
+ };
+
scaler_0: scaler@12800000 {
compatible = "samsung,exynos5420-scaler";
reg = <0x12800000 0x1294>;
@@ -1042,7 +1092,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
clock-names = "bus";
- operating-points-v2 = <&bus_wcore_opp_table>;
status = "disabled";
};
@@ -1050,7 +1099,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK100_NOC>;
clock-names = "bus";
- operating-points-v2 = <&bus_noc_opp_table>;
status = "disabled";
};
@@ -1058,7 +1106,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
clock-names = "bus";
- operating-points-v2 = <&bus_fsys_apb_opp_table>;
status = "disabled";
};
@@ -1066,7 +1113,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
clock-names = "bus";
- operating-points-v2 = <&bus_fsys_apb_opp_table>;
status = "disabled";
};
@@ -1074,7 +1120,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
clock-names = "bus";
- operating-points-v2 = <&bus_fsys2_opp_table>;
status = "disabled";
};
@@ -1082,7 +1127,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK333>;
clock-names = "bus";
- operating-points-v2 = <&bus_mfc_opp_table>;
status = "disabled";
};
@@ -1090,7 +1134,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK266>;
clock-names = "bus";
- operating-points-v2 = <&bus_gen_opp_table>;
status = "disabled";
};
@@ -1098,7 +1141,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK66>;
clock-names = "bus";
- operating-points-v2 = <&bus_peri_opp_table>;
status = "disabled";
};
@@ -1106,7 +1148,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK333_G2D>;
clock-names = "bus";
- operating-points-v2 = <&bus_g2d_opp_table>;
status = "disabled";
};
@@ -1114,7 +1155,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK266_G2D>;
clock-names = "bus";
- operating-points-v2 = <&bus_g2d_acp_opp_table>;
status = "disabled";
};
@@ -1122,7 +1162,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
clock-names = "bus";
- operating-points-v2 = <&bus_jpeg_opp_table>;
status = "disabled";
};
@@ -1130,7 +1169,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK166>;
clock-names = "bus";
- operating-points-v2 = <&bus_jpeg_apb_opp_table>;
status = "disabled";
};
@@ -1138,7 +1176,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
clock-names = "bus";
- operating-points-v2 = <&bus_disp1_fimd_opp_table>;
status = "disabled";
};
@@ -1146,7 +1183,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
clock-names = "bus";
- operating-points-v2 = <&bus_disp1_opp_table>;
status = "disabled";
};
@@ -1154,7 +1190,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
clock-names = "bus";
- operating-points-v2 = <&bus_gscl_opp_table>;
status = "disabled";
};
@@ -1162,252 +1197,8 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
clock-names = "bus";
- operating-points-v2 = <&bus_mscl_opp_table>;
status = "disabled";
};
-
- bus_wcore_opp_table: opp_table2 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <84000000>;
- opp-microvolt = <925000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <111000000>;
- opp-microvolt = <950000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <222000000>;
- opp-microvolt = <950000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <333000000>;
- opp-microvolt = <950000>;
- };
- opp04 {
- opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <987500>;
- };
- };
-
- bus_noc_opp_table: opp_table3 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <67000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <75000000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <86000000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <100000000>;
- };
- };
-
- bus_fsys_apb_opp_table: opp_table4 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp00 {
- opp-hz = /bits/ 64 <100000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <200000000>;
- };
- };
-
- bus_fsys2_opp_table: opp_table5 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <75000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <100000000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <150000000>;
- };
- };
-
- bus_mfc_opp_table: opp_table6 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <96000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <111000000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <167000000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <222000000>;
- };
- opp04 {
- opp-hz = /bits/ 64 <333000000>;
- };
- };
-
- bus_gen_opp_table: opp_table7 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <89000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <133000000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <178000000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <267000000>;
- };
- };
-
- bus_peri_opp_table: opp_table8 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <67000000>;
- };
- };
-
- bus_g2d_opp_table: opp_table9 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <84000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <167000000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <222000000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <300000000>;
- };
- opp04 {
- opp-hz = /bits/ 64 <333000000>;
- };
- };
-
- bus_g2d_acp_opp_table: opp_table10 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <67000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <133000000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <178000000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <267000000>;
- };
- };
-
- bus_jpeg_opp_table: opp_table11 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <75000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <150000000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <200000000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <300000000>;
- };
- };
-
- bus_jpeg_apb_opp_table: opp_table12 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <84000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <111000000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <134000000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <167000000>;
- };
- };
-
- bus_disp1_fimd_opp_table: opp_table13 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <120000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <200000000>;
- };
- };
-
- bus_disp1_opp_table: opp_table14 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <120000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <200000000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <300000000>;
- };
- };
-
- bus_gscl_opp_table: opp_table15 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <150000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <200000000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <300000000>;
- };
- };
-
- bus_mscl_opp_table: opp_table16 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <84000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <167000000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <222000000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <333000000>;
- };
- opp04 {
- opp-hz = /bits/ 64 <400000000>;
- };
- };
};
thermal-zones {
diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
index e4a5857c135f..1b8605cf2407 100644
--- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * SAMSUNG EXYNOS5422 SoC cpu device tree source
+ * Samsung Exynos5422 SoC cpu device tree source
*
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 059fa32d1a8f..5cf1aed20490 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -35,7 +35,264 @@
};
};
- dmc_opp_table: opp_table2 {
+ bus_wcore_opp_table: opp_table2 {
+ compatible = "operating-points-v2";
+
+ /* derived from 532MHz MPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <88700000>;
+ opp-microvolt = <925000 925000 1400000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <133000000>;
+ opp-microvolt = <950000 950000 1400000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <177400000>;
+ opp-microvolt = <950000 950000 1400000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <266000000>;
+ opp-microvolt = <950000 950000 1400000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <532000000>;
+ opp-microvolt = <1000000 1000000 1400000>;
+ };
+ };
+
+ bus_noc_opp_table: opp_table3 {
+ compatible = "operating-points-v2";
+
+ /* derived from 666MHz CPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <66600000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <74000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <83250000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <111000000>;
+ };
+ };
+
+ bus_fsys_apb_opp_table: opp_table4 {
+ compatible = "operating-points-v2";
+
+ /* derived from 666MHz CPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <111000000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <222000000>;
+ };
+ };
+
+ bus_fsys2_opp_table: opp_table5 {
+ compatible = "operating-points-v2";
+
+ /* derived from 600MHz DPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <75000000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <120000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <200000000>;
+ };
+ };
+
+ bus_mfc_opp_table: opp_table6 {
+ compatible = "operating-points-v2";
+
+ /* derived from 666MHz CPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <83250000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <111000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <166500000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <222000000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <333000000>;
+ };
+ };
+
+ bus_gen_opp_table: opp_table7 {
+ compatible = "operating-points-v2";
+
+ /* derived from 532MHz MPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <88700000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <133000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <178000000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <266000000>;
+ };
+ };
+
+ bus_peri_opp_table: opp_table8 {
+ compatible = "operating-points-v2";
+
+ /* derived from 666MHz CPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <66600000>;
+ };
+ };
+
+ bus_g2d_opp_table: opp_table9 {
+ compatible = "operating-points-v2";
+
+ /* derived from 666MHz CPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <83250000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <111000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <166500000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <222000000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <333000000>;
+ };
+ };
+
+ bus_g2d_acp_opp_table: opp_table10 {
+ compatible = "operating-points-v2";
+
+ /* derived from 532MHz MPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <66500000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <133000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <178000000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <266000000>;
+ };
+ };
+
+ bus_jpeg_opp_table: opp_table11 {
+ compatible = "operating-points-v2";
+
+ /* derived from 600MHz DPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <75000000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <150000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <200000000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <300000000>;
+ };
+ };
+
+ bus_jpeg_apb_opp_table: opp_table12 {
+ compatible = "operating-points-v2";
+
+ /* derived from 666MHz CPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <83250000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <111000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <133000000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <166500000>;
+ };
+ };
+
+ bus_disp1_fimd_opp_table: opp_table13 {
+ compatible = "operating-points-v2";
+
+ /* derived from 600MHz DPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <120000000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <200000000>;
+ };
+ };
+
+ bus_disp1_opp_table: opp_table14 {
+ compatible = "operating-points-v2";
+
+ /* derived from 600MHz DPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <120000000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <200000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <300000000>;
+ };
+ };
+
+ bus_gscl_opp_table: opp_table15 {
+ compatible = "operating-points-v2";
+
+ /* derived from 600MHz DPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <150000000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <200000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <300000000>;
+ };
+ };
+
+ bus_mscl_opp_table: opp_table16 {
+ compatible = "operating-points-v2";
+
+ /* derived from 666MHz CPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <84000000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <167000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <222000000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <333000000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <666000000>;
+ };
+ };
+
+ dmc_opp_table: opp_table17 {
compatible = "operating-points-v2";
opp00 {
@@ -134,6 +391,7 @@
};
&bus_wcore {
+ operating-points-v2 = <&bus_wcore_opp_table>;
devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
<&nocp_mem1_0>, <&nocp_mem1_1>;
vdd-supply = <&buck3_reg>;
@@ -142,76 +400,91 @@
};
&bus_noc {
+ operating-points-v2 = <&bus_noc_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_fsys_apb {
+ operating-points-v2 = <&bus_fsys_apb_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_fsys {
+ operating-points-v2 = <&bus_fsys2_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_fsys2 {
+ operating-points-v2 = <&bus_fsys2_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_mfc {
+ operating-points-v2 = <&bus_mfc_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_gen {
+ operating-points-v2 = <&bus_gen_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_peri {
+ operating-points-v2 = <&bus_peri_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_g2d {
+ operating-points-v2 = <&bus_g2d_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_g2d_acp {
+ operating-points-v2 = <&bus_g2d_acp_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_jpeg {
+ operating-points-v2 = <&bus_jpeg_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_jpeg_apb {
+ operating-points-v2 = <&bus_jpeg_apb_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_disp1_fimd {
+ operating-points-v2 = <&bus_disp1_fimd_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_disp1 {
+ operating-points-v2 = <&bus_disp1_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_gscl_scaler {
+ operating-points-v2 = <&bus_gscl_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_mscl {
+ operating-points-v2 = <&bus_mscl_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
@@ -601,6 +874,8 @@
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&buck3_reg>;
+ regulator-coupled-max-spread = <300000>;
regulator-state-mem {
regulator-off-in-suspend;
@@ -613,6 +888,8 @@
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&buck2_reg>;
+ regulator-coupled-max-spread = <300000>;
regulator-state-mem {
regulator-off-in-suspend;
@@ -623,7 +900,6 @@
regulator-name = "vdd_g3d";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
- regulator-always-on;
regulator-boot-on;
regulator-state-mem {
@@ -771,6 +1047,11 @@
vtmu-supply = <&ldo7_reg>;
};
+&gpu {
+ mali-supply = <&buck4_reg>;
+ status = "okay";
+};
+
&rtc {
status = "okay";
clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/exynos5422-odroidhc1.dts
index d271e7548826..f163206265bb 100644
--- a/arch/arm/boot/dts/exynos5422-odroidhc1.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidhc1.dts
@@ -72,14 +72,14 @@
*/
map1 {
trip = <&cpu0_alert1>;
- cooling-device = <&cpu0 3 7>,
- <&cpu1 3 7>,
- <&cpu2 3 7>,
- <&cpu3 3 7>,
- <&cpu4 3 12>,
- <&cpu5 3 12>,
- <&cpu6 3 12>,
- <&cpu7 3 12>;
+ cooling-device = <&cpu0 3 8>,
+ <&cpu1 3 8>,
+ <&cpu2 3 8>,
+ <&cpu3 3 8>,
+ <&cpu4 3 14>,
+ <&cpu5 3 14>,
+ <&cpu6 3 14>,
+ <&cpu7 3 14>;
};
};
};
@@ -116,14 +116,14 @@
};
map1 {
trip = <&cpu1_alert1>;
- cooling-device = <&cpu0 3 7>,
- <&cpu1 3 7>,
- <&cpu2 3 7>,
- <&cpu3 3 7>,
- <&cpu4 3 12>,
- <&cpu5 3 12>,
- <&cpu6 3 12>,
- <&cpu7 3 12>;
+ cooling-device = <&cpu0 3 8>,
+ <&cpu1 3 8>,
+ <&cpu2 3 8>,
+ <&cpu3 3 8>,
+ <&cpu4 3 14>,
+ <&cpu5 3 14>,
+ <&cpu6 3 14>,
+ <&cpu7 3 14>;
};
};
};
@@ -160,14 +160,14 @@
};
map1 {
trip = <&cpu2_alert1>;
- cooling-device = <&cpu0 3 7>,
- <&cpu1 3 7>,
- <&cpu2 3 7>,
- <&cpu3 3 7>,
- <&cpu4 3 12>,
- <&cpu5 3 12>,
- <&cpu6 3 12>,
- <&cpu7 3 12>;
+ cooling-device = <&cpu0 3 8>,
+ <&cpu1 3 8>,
+ <&cpu2 3 8>,
+ <&cpu3 3 8>,
+ <&cpu4 3 14>,
+ <&cpu5 3 14>,
+ <&cpu6 3 14>,
+ <&cpu7 3 14>;
};
};
};
@@ -204,14 +204,14 @@
};
map1 {
trip = <&cpu3_alert1>;
- cooling-device = <&cpu0 3 7>,
- <&cpu1 3 7>,
- <&cpu2 3 7>,
- <&cpu3 3 7>,
- <&cpu4 3 12>,
- <&cpu5 3 12>,
- <&cpu6 3 12>,
- <&cpu7 3 12>;
+ cooling-device = <&cpu0 3 8>,
+ <&cpu1 3 8>,
+ <&cpu2 3 8>,
+ <&cpu3 3 8>,
+ <&cpu4 3 14>,
+ <&cpu5 3 14>,
+ <&cpu6 3 14>,
+ <&cpu7 3 14>;
};
};
};
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
index 838872037493..1865a708b49f 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
@@ -107,7 +107,7 @@
/*
* When reaching cpu0_alert3, reduce CPU
* by 2 steps. On Exynos5422/5800 that would
- * be: 1600 MHz and 1100 MHz.
+ * (usually) be: 1800 MHz and 1200 MHz.
*/
map3 {
trip = <&cpu0_alert3>;
@@ -122,19 +122,19 @@
};
/*
* When reaching cpu0_alert4, reduce CPU
- * further, down to 600 MHz (12 steps for big,
- * 7 steps for LITTLE).
+ * further, down to 600 MHz (14 steps for big,
+ * 8 steps for LITTLE).
*/
- map4 {
+ cpu0_cooling_map4: map4 {
trip = <&cpu0_alert4>;
- cooling-device = <&cpu0 3 7>,
- <&cpu1 3 7>,
- <&cpu2 3 7>,
- <&cpu3 3 7>,
- <&cpu4 3 12>,
- <&cpu5 3 12>,
- <&cpu6 3 12>,
- <&cpu7 3 12>;
+ cooling-device = <&cpu0 3 8>,
+ <&cpu1 3 8>,
+ <&cpu2 3 8>,
+ <&cpu3 3 8>,
+ <&cpu4 3 14>,
+ <&cpu5 3 14>,
+ <&cpu6 3 14>,
+ <&cpu7 3 14>;
};
};
};
@@ -198,16 +198,16 @@
<&cpu6 0 2>,
<&cpu7 0 2>;
};
- map4 {
+ cpu1_cooling_map4: map4 {
trip = <&cpu1_alert4>;
- cooling-device = <&cpu0 3 7>,
- <&cpu1 3 7>,
- <&cpu2 3 7>,
- <&cpu3 3 7>,
- <&cpu4 3 12>,
- <&cpu5 3 12>,
- <&cpu6 3 12>,
- <&cpu7 3 12>;
+ cooling-device = <&cpu0 3 8>,
+ <&cpu1 3 8>,
+ <&cpu2 3 8>,
+ <&cpu3 3 8>,
+ <&cpu4 3 14>,
+ <&cpu5 3 14>,
+ <&cpu6 3 14>,
+ <&cpu7 3 14>;
};
};
};
@@ -271,16 +271,16 @@
<&cpu6 0 2>,
<&cpu7 0 2>;
};
- map4 {
+ cpu2_cooling_map4: map4 {
trip = <&cpu2_alert4>;
- cooling-device = <&cpu0 3 7>,
- <&cpu1 3 7>,
- <&cpu2 3 7>,
- <&cpu3 3 7>,
- <&cpu4 3 12>,
- <&cpu5 3 12>,
- <&cpu6 3 12>,
- <&cpu7 3 12>;
+ cooling-device = <&cpu0 3 8>,
+ <&cpu1 3 8>,
+ <&cpu2 3 8>,
+ <&cpu3 3 8>,
+ <&cpu4 3 14>,
+ <&cpu5 3 14>,
+ <&cpu6 3 14>,
+ <&cpu7 3 14>;
};
};
};
@@ -344,16 +344,16 @@
<&cpu6 0 2>,
<&cpu7 0 2>;
};
- map4 {
+ cpu3_cooling_map4: map4 {
trip = <&cpu3_alert4>;
- cooling-device = <&cpu0 3 7>,
- <&cpu1 3 7>,
- <&cpu2 3 7>,
- <&cpu3 3 7>,
- <&cpu4 3 12>,
- <&cpu5 3 12>,
- <&cpu6 3 12>,
- <&cpu7 3 12>;
+ cooling-device = <&cpu0 3 8>,
+ <&cpu1 3 8>,
+ <&cpu2 3 8>,
+ <&cpu3 3 8>,
+ <&cpu4 3 14>,
+ <&cpu5 3 14>,
+ <&cpu6 3 14>,
+ <&cpu7 3 14>;
};
};
};
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
index a31ca2ef750f..98feecad5489 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
@@ -30,6 +30,64 @@
samsung,asv-bin = <2>;
};
+/*
+ * Odroid XU3-Lite board uses SoC revision with lower maximum frequencies
+ * than Odroid XU3/XU4 boards: 1.8 GHz for A15 cores & 1.3 GHz for A7 cores.
+ * Therefore we need to update OPPs tables and thermal maps accordingly.
+ */
+&cluster_a15_opp_table {
+ /delete-node/opp-2000000000;
+ /delete-node/opp-1900000000;
+};
+
+&cluster_a7_opp_table {
+ /delete-node/opp-1400000000;
+};
+
+&cpu0_cooling_map4 {
+ cooling-device = <&cpu0 3 7>,
+ <&cpu1 3 7>,
+ <&cpu2 3 7>,
+ <&cpu3 3 7>,
+ <&cpu4 3 12>,
+ <&cpu5 3 12>,
+ <&cpu6 3 12>,
+ <&cpu7 3 12>;
+};
+
+&cpu1_cooling_map4 {
+ cooling-device = <&cpu0 3 7>,
+ <&cpu1 3 7>,
+ <&cpu2 3 7>,
+ <&cpu3 3 7>,
+ <&cpu4 3 12>,
+ <&cpu5 3 12>,
+ <&cpu6 3 12>,
+ <&cpu7 3 12>;
+};
+
+&cpu2_cooling_map4 {
+ cooling-device = <&cpu0 3 7>,
+ <&cpu1 3 7>,
+ <&cpu2 3 7>,
+ <&cpu3 3 7>,
+ <&cpu4 3 12>,
+ <&cpu5 3 12>,
+ <&cpu6 3 12>,
+ <&cpu7 3 12>;
+};
+
+&cpu3_cooling_map4 {
+ cooling-device = <&cpu0 3 7>,
+ <&cpu1 3 7>,
+ <&cpu2 3 7>,
+ <&cpu3 3 7>,
+ <&cpu4 3 12>,
+ <&cpu5 3 12>,
+ <&cpu6 3 12>,
+ <&cpu7 3 12>;
+};
+
&pwm {
/*
* PWM 0 -- fan
diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi
index f78dee801cd9..8aa5117e58ce 100644
--- a/arch/arm/boot/dts/exynos54xx.dtsi
+++ b/arch/arm/boot/dts/exynos54xx.dtsi
@@ -62,12 +62,12 @@
#size-cells = <1>;
ranges = <0 0x02020000 0x54000>;
- smp-sysram@0 {
+ smp-sram@0 {
compatible = "samsung,exynos4210-sysram";
reg = <0x0 0x1000>;
};
- smp-sysram@53000 {
+ smp-sram@53000 {
compatible = "samsung,exynos4210-sysram-ns";
reg = <0x53000 0x1000>;
};
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 60ca3d685247..60ab0effe474 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -156,6 +156,15 @@
assigned-clock-parents = <&clock CLK_MAU_EPLL>;
};
+/*
+ * Peach Pi board uses SoC revision with lower maximum frequency for A7 cores
+ * (1.3 GHz instead of 1.4 GHz) than Odroid XU3/XU4 boards. Thus we need to
+ * update A7 OPPs table accordingly.
+ */
+&cluster_a7_opp_table {
+ /delete-node/opp-1400000000;
+};
+
&cpu0 {
cpu-supply = <&buck2_reg>;
};
@@ -257,6 +266,8 @@
regulator-always-on;
regulator-boot-on;
regulator-ramp-delay = <12500>;
+ regulator-coupled-with = <&buck3_reg>;
+ regulator-coupled-max-spread = <300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
@@ -269,6 +280,8 @@
regulator-always-on;
regulator-boot-on;
regulator-ramp-delay = <12500>;
+ regulator-coupled-with = <&buck2_reg>;
+ regulator-coupled-max-spread = <300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi
index 16177d815ee4..dfb99ab53c3e 100644
--- a/arch/arm/boot/dts/exynos5800.dtsi
+++ b/arch/arm/boot/dts/exynos5800.dtsi
@@ -1,12 +1,12 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * SAMSUNG EXYNOS5800 SoC device tree source
+ * Samsung Exynos5800 SoC device tree source
*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
- * SAMSUNG EXYNOS5800 SoC device nodes are listed in this file.
- * EXYNOS5800 based board files can include this file and provide
+ * Samsung Exynos5800 SoC device nodes are listed in this file.
+ * Exynos5800 based board files can include this file and provide
* values for board specfic bindings.
*/
@@ -21,67 +21,87 @@
};
&cluster_a15_opp_table {
+ opp-2000000000 {
+ opp-hz = /bits/ 64 <2000000000>;
+ opp-microvolt = <1312500>;
+ clock-latency-ns = <140000>;
+ };
+ opp-1900000000 {
+ opp-hz = /bits/ 64 <1900000000>;
+ opp-microvolt = <1262500>;
+ clock-latency-ns = <140000>;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1237500>;
+ clock-latency-ns = <140000>;
+ };
opp-1700000000 {
- opp-microvolt = <1250000>;
+ opp-microvolt = <1250000 1250000 1500000>;
};
opp-1600000000 {
- opp-microvolt = <1250000>;
+ opp-microvolt = <1250000 1250000 1500000>;
};
opp-1500000000 {
- opp-microvolt = <1100000>;
+ opp-microvolt = <1100000 1100000 1500000>;
};
opp-1400000000 {
- opp-microvolt = <1100000>;
+ opp-microvolt = <1100000 1100000 1500000>;
};
opp-1300000000 {
- opp-microvolt = <1100000>;
+ opp-microvolt = <1100000 1100000 1500000>;
};
opp-1200000000 {
- opp-microvolt = <1000000>;
+ opp-microvolt = <1000000 1000000 1500000>;
};
opp-1100000000 {
- opp-microvolt = <1000000>;
+ opp-microvolt = <1000000 1000000 1500000>;
};
opp-1000000000 {
- opp-microvolt = <1000000>;
+ opp-microvolt = <1000000 1000000 1500000>;
};
opp-900000000 {
- opp-microvolt = <1000000>;
+ opp-microvolt = <1000000 1000000 1500000>;
};
opp-800000000 {
- opp-microvolt = <900000>;
+ opp-microvolt = <900000 900000 1500000>;
};
opp-700000000 {
- opp-microvolt = <900000>;
+ opp-microvolt = <900000 900000 1500000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <900000 900000 1500000>;
clock-latency-ns = <140000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <900000 900000 1500000>;
clock-latency-ns = <140000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <900000 900000 1500000>;
clock-latency-ns = <140000>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <900000 900000 1500000>;
clock-latency-ns = <140000>;
};
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <900000 900000 1500000>;
clock-latency-ns = <140000>;
};
};
&cluster_a7_opp_table {
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt = <1275000>;
+ clock-latency-ns = <140000>;
+ };
opp-1300000000 {
opp-microvolt = <1250000>;
};
diff --git a/arch/arm/boot/dts/ibm-power9-dual.dtsi b/arch/arm/boot/dts/ibm-power9-dual.dtsi
index 2abc42eda7b0..a0fa65b44b0f 100644
--- a/arch/arm/boot/dts/ibm-power9-dual.dtsi
+++ b/arch/arm/boot/dts/ibm-power9-dual.dtsi
@@ -86,7 +86,7 @@
#address-cells = <1>;
#size-cells = <0>;
- fsi_occ0: occ {
+ fsi_occ0: occ@1 {
compatible = "ibm,p9-occ";
};
};
@@ -187,7 +187,7 @@
#address-cells = <1>;
#size-cells = <0>;
- fsi_occ1: occ {
+ fsi_occ1: occ@2 {
compatible = "ibm,p9-occ";
};
};
diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
index 0fde90df2b54..3f38c2e60a74 100644
--- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
+++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
@@ -165,8 +165,6 @@
};
&usbhost1 {
- phy_type = "serial";
- dr_mode = "host";
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
index 05cccd12624c..fb66884d8a2f 100644
--- a/arch/arm/boot/dts/imx25-pdk.dts
+++ b/arch/arm/boot/dts/imx25-pdk.dts
@@ -304,8 +304,6 @@
};
&usbhost1 {
- phy_type = "serial";
- dr_mode = "host";
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index 9a097ef014af..40b95a290bd6 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -570,6 +570,9 @@
clock-names = "ipg", "ahb", "per";
fsl,usbmisc = <&usbmisc 1>;
fsl,usbphy = <&usbphy1>;
+ maximum-speed = "full-speed";
+ phy_type = "serial";
+ dr_mode = "host";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index ed6a3ce874b2..552196d8a60a 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -58,29 +58,27 @@
display1: disp1 {
compatible = "fsl,imx-parallel-display";
+ #address-cells = <1>;
+ #size-cells = <0>;
interface-pix-fmt = "rgb24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp1>;
- display-timings {
- native-mode = <&timing0>;
- timing0: dvi {
- clock-frequency = <65000000>;
- hactive = <1024>;
- vactive = <768>;
- hback-porch = <220>;
- hfront-porch = <40>;
- vback-porch = <21>;
- vfront-porch = <7>;
- hsync-len = <60>;
- vsync-len = <10>;
- };
- };
- port {
+ port@0 {
+ reg = <0>;
+
display0_in: endpoint {
remote-endpoint = <&ipu_di0_disp1>;
};
};
+
+ port@1 {
+ reg = <1>;
+
+ parallel_display_out: endpoint {
+ remote-endpoint = <&tfp410_in>;
+ };
+ };
};
display2: disp2 {
@@ -115,6 +113,42 @@
};
};
+ dvi-connector {
+ compatible = "dvi-connector";
+ digital;
+
+ port {
+ dvi_connector_in: endpoint {
+ remote-endpoint = <&tfp410_out>;
+ };
+ };
+ };
+
+ dvi-encoder {
+ compatible = "ti,tfp410";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tfp410_in: endpoint {
+ remote-endpoint = <&parallel_display_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tfp410_out: endpoint {
+ remote-endpoint = <&dvi_connector_in>;
+ };
+ };
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/imx6dl-gw5907.dts b/arch/arm/boot/dts/imx6dl-gw5907.dts
new file mode 100644
index 000000000000..3fa2822beffc
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-gw5907.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-gw5907.dtsi"
+
+/ {
+ model = "Gateworks Ventana i.MX6 DualLite/Solo GW5907";
+ compatible = "gw,imx6dl-gw5907", "gw,ventana", "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/imx6dl-gw5910.dts b/arch/arm/boot/dts/imx6dl-gw5910.dts
new file mode 100644
index 000000000000..0d5e7e5da536
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-gw5910.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-gw5910.dtsi"
+
+/ {
+ model = "Gateworks Ventana i.MX6 DualLite/Solo GW5910";
+ compatible = "gw,imx6dl-gw5910", "gw,ventana", "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/imx6dl-gw5912.dts b/arch/arm/boot/dts/imx6dl-gw5912.dts
new file mode 100644
index 000000000000..5260e0142d63
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-gw5912.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Gateworks Corporation
+ */
+
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-gw5912.dtsi"
+
+/ {
+ model = "Gateworks Ventana i.MX6 DualLite/Solo GW5912";
+ compatible = "gw,imx6dl-gw5912", "gw,ventana", "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/imx6dl-gw5913.dts b/arch/arm/boot/dts/imx6dl-gw5913.dts
new file mode 100644
index 000000000000..b74e533c8e67
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-gw5913.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-gw5913.dtsi"
+
+/ {
+ model = "Gateworks Ventana i.MX6 DualLite/Solo GW5913";
+ compatible = "gw,imx6dl-gw5913", "gw,ventana", "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/imx6q-gw5907.dts b/arch/arm/boot/dts/imx6q-gw5907.dts
new file mode 100644
index 000000000000..b25526ef5886
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-gw5907.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-gw5907.dtsi"
+
+/ {
+ model = "Gateworks Ventana i.MX6 Dual/Quad GW5907";
+ compatible = "gw,imx6q-gw5907", "gw,ventana", "fsl,imx6q";
+};
diff --git a/arch/arm/boot/dts/imx6q-gw5910.dts b/arch/arm/boot/dts/imx6q-gw5910.dts
new file mode 100644
index 000000000000..6aafa2fcee08
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-gw5910.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-gw5910.dtsi"
+
+/ {
+ model = "Gateworks Ventana i.MX6 Dual/Quad GW5910";
+ compatible = "gw,imx6q-gw5910", "gw,ventana", "fsl,imx6q";
+};
diff --git a/arch/arm/boot/dts/imx6q-gw5912.dts b/arch/arm/boot/dts/imx6q-gw5912.dts
new file mode 100644
index 000000000000..4dcbd943cd93
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-gw5912.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Gateworks Corporation
+ */
+
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-gw5912.dtsi"
+
+/ {
+ model = "Gateworks Ventana i.MX6 Dual/Quad GW5912";
+ compatible = "gw,imx6q-gw5912", "gw,ventana", "fsl,imx6q";
+};
diff --git a/arch/arm/boot/dts/imx6q-gw5913.dts b/arch/arm/boot/dts/imx6q-gw5913.dts
new file mode 100644
index 000000000000..6f511f1665fd
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-gw5913.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-gw5913.dtsi"
+
+/ {
+ model = "Gateworks Ventana i.MX6 Dual/Quad GW5913";
+ compatible = "gw,imx6q-gw5913", "gw,ventana", "fsl,imx6q";
+};
diff --git a/arch/arm/boot/dts/imx6q-logicpd.dts b/arch/arm/boot/dts/imx6q-logicpd.dts
index d96ae54be338..7a3d1d3e54a9 100644
--- a/arch/arm/boot/dts/imx6q-logicpd.dts
+++ b/arch/arm/boot/dts/imx6q-logicpd.dts
@@ -73,6 +73,16 @@
status = "okay";
};
+&i2c1 {
+ touchscreen@26 {
+ compatible = "ilitek,ili2117";
+ reg = <0x26>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touchscreen>;
+ interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_RISING>;
+ };
+};
+
&ldb {
status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
index ff1287e6b7ce..1b5bc6b5e806 100644
--- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
@@ -200,7 +200,7 @@
&hdmi {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hdmi_ddc>;
+ pinctrl-0 = <&pinctrl_hdmi_ddc &pinctrl_hdmi_cec>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/imx6qdl-gw5907.dtsi b/arch/arm/boot/dts/imx6qdl-gw5907.dtsi
new file mode 100644
index 000000000000..0bdebddffd51
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-gw5907.dtsi
@@ -0,0 +1,399 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ /* these are used by bootloader for disabling nodes */
+ aliases {
+ led0 = &led0;
+ led1 = &led1;
+ nand = &gpmi;
+ usb0 = &usbh1;
+ usb1 = &usbotg;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led0: user1 {
+ label = "user1";
+ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led1: user2 {
+ label = "user2";
+ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
+ default-state = "off";
+ };
+ };
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x20000000>;
+ };
+
+ pps {
+ compatible = "pps-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pps>;
+ gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_5p0v: regulator-5p0v {
+ compatible = "regulator-fixed";
+ regulator-name = "5P0V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii-id";
+ phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c3>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ gpio@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+
+ eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <16>;
+ };
+
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1672";
+ reg = <0x68>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ gpio@20 {
+ compatible = "nxp,pca9555";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ adc@48 {
+ compatible = "ti,ads1015";
+ reg = <0x48>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@4 {
+ reg = <4>;
+ ti,gain = <0>;
+ ti,datarate = <5>;
+ };
+
+ channel@5 {
+ reg = <5>;
+ ti,gain = <0>;
+ ti,datarate = <5>;
+ };
+
+ channel@6 {
+ reg = <6>;
+ ti,gain = <0>;
+ ti,datarate = <5>;
+ };
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
+ status = "disabled";
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
+ status = "disabled";
+};
+
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
+ status = "disabled";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <&reg_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+};
+
+&iomuxc {
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpmi_nand: gpminandgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
+ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
+ >;
+ };
+
+ pinctrl_pps: ppsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
new file mode 100644
index 000000000000..be1af7482f89
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
@@ -0,0 +1,491 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ /* these are used by bootloader for disabling nodes */
+ aliases {
+ led0 = &led0;
+ led1 = &led1;
+ led2 = &led2;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x20000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led0: user1 {
+ label = "user1";
+ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led1: user2 {
+ label = "user2";
+ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
+ default-state = "off";
+ };
+
+ led2: user3 {
+ label = "user3";
+ gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
+ default-state = "off";
+ };
+ };
+
+ pps {
+ compatible = "pps-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pps>;
+ gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_5p0v: regulator-5p0v {
+ compatible = "regulator-fixed";
+ regulator-name = "5P0V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ reg_wl: regulator-wl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_wl>;
+ compatible = "regulator-fixed";
+ regulator-name = "wl";
+ gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <100>;
+ enable-active-high;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_bt: regulator-bt {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_bt>;
+ compatible = "regulator-fixed";
+ regulator-name = "bt";
+ gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <100>;
+ enable-active-high;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+};
+
+
+&ecspi3 {
+ cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3>;
+ status = "okay";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ gpio@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+
+ eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <16>;
+ };
+
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1672";
+ reg = <0x68>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ accel@19 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_accel>;
+ compatible = "st,lis2de12";
+ reg = <0x19>;
+ st,drdy-int-pin = <1>;
+ interrupt-parent = <&gpio7>;
+ interrupts = <13 0>;
+ interrupt-names = "INT1";
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
+ status = "disabled";
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
+ status = "disabled";
+};
+
+/* off-board RS232 */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+/* serial console */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+/* Sterling-LWB Bluetooth */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+/* GPS */
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <&reg_5p0v>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+/* Sterling-LWB SDIO WiFi */
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ vmmc-supply = <&reg_3p3v>;
+ non-removable;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&reg_3p3v>;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+};
+
+&iomuxc {
+ pinctrl_accel: accelmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
+ >;
+ };
+
+ pinctrl_ecspi3: escpi3grp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
+ MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
+ MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
+ MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpmi_nand: gpminandgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
+ >;
+ };
+
+ pinctrl_pps: ppsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_reg_bt: regbtgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1
+ >;
+ };
+
+ pinctrl_reg_wl: regwlgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-gw5912.dtsi b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi
new file mode 100644
index 000000000000..8c57fd2f9a0b
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi
@@ -0,0 +1,461 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ /* these are used by bootloader for disabling nodes */
+ aliases {
+ led0 = &led0;
+ led1 = &led1;
+ led2 = &led2;
+ nand = &gpmi;
+ usb0 = &usbh1;
+ usb1 = &usbotg;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led0: user1 {
+ label = "user1";
+ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led1: user2 {
+ label = "user2";
+ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
+ default-state = "off";
+ };
+
+ led2: user3 {
+ label = "user3";
+ gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
+ default-state = "off";
+ };
+ };
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x40000000>;
+ };
+
+ pps {
+ compatible = "pps-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pps>;
+ gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_usb_vbus: regulator-5p0v {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "okay";
+};
+
+&ecspi2 {
+ cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ status = "okay";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ gpio@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+
+ eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <16>;
+ };
+
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1672";
+ reg = <0x68>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ accel@19 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_accel>;
+ compatible = "st,lis2de12";
+ reg = <0x19>;
+ st,drdy-int-pin = <1>;
+ interrupt-parent = <&gpio7>;
+ interrupts = <13 0>;
+ interrupt-names = "INT1";
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
+ status = "disabled";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
+ status = "disabled";
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
+ status = "disabled";
+};
+
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
+ status = "disabled";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ rts-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <&reg_usb_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <&reg_usb_vbus>;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&reg_3p3v>;
+ no-1-8-v; /* firmware will remove if board revision supports */
+ status = "okay";
+};
+
+&wdog1 {
+ status = "disabled";
+};
+
+&wdog2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_accel: accelmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ >;
+ };
+
+ pinctrl_ecspi2: escpi2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
+ MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
+ MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
+ MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpmi_nand: gpminandgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
+ >;
+ };
+
+ pinctrl_pps: ppsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b1
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-gw5913.dtsi b/arch/arm/boot/dts/imx6qdl-gw5913.dtsi
new file mode 100644
index 000000000000..635c203bd64d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-gw5913.dtsi
@@ -0,0 +1,348 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ /* these are used by bootloader for disabling nodes */
+ aliases {
+ led0 = &led0;
+ led1 = &led1;
+ nand = &gpmi;
+ usb0 = &usbh1;
+ usb1 = &usbotg;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led0: user1 {
+ label = "user1";
+ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led1: user2 {
+ label = "user2";
+ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
+ default-state = "off";
+ };
+ };
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x20000000>;
+ };
+
+ pps {
+ compatible = "pps-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pps>;
+ gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_5p0v: regulator-5p0v {
+ compatible = "regulator-fixed";
+ regulator-name = "5P0V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ gpio@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+
+ eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <16>;
+ };
+
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1672";
+ reg = <0x68>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
+ status = "disabled";
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
+ status = "disabled";
+};
+
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
+ status = "disabled";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ status = "okay";
+};
+
+&usbotg {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+};
+
+&iomuxc {
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpmi_nand: gpminandgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
+ >;
+ };
+
+ pinctrl_pps: ppsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi b/arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi
index d91d46b5898f..0fd7f2e24d9c 100644
--- a/arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi
@@ -25,10 +25,8 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
- phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
clocks = <&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET_REF>;
- phy-mode = "rmii";
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi
index 7814f1ef0804..756f3a9f1b4f 100644
--- a/arch/arm/boot/dts/imx6qdl-icore.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi
@@ -150,10 +150,23 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
- phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>;
phy-mode = "rmii";
+ phy-handle = <&eth_phy>;
status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eth_phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <4000>;
+ reset-deassert-us = <4000>;
+ };
+ };
};
&gpmi {
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
index 6486df3e2942..978dc1c2ff1b 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
@@ -5,6 +5,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/dlg,da9063-regulator.h>
/ {
aliases {
@@ -100,6 +101,10 @@
compatible = "dlg,da9062-rtc";
};
+ da9062_onkey: onkey {
+ compatible = "dlg,da9062-onkey";
+ };
+
watchdog {
compatible = "dlg,da9062-watchdog";
};
@@ -109,6 +114,7 @@
regulator-name = "vdd_arm";
regulator-min-microvolt = <730000>;
regulator-max-microvolt = <1380000>;
+ regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
regulator-always-on;
};
@@ -116,6 +122,7 @@
regulator-name = "vdd_soc";
regulator-min-microvolt = <730000>;
regulator-max-microvolt = <1380000>;
+ regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
regulator-always-on;
};
@@ -123,6 +130,7 @@
regulator-name = "vdd_ddr3";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
+ regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
regulator-always-on;
};
@@ -130,6 +138,7 @@
regulator-name = "vdd_eth";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
regulator-always-on;
};
diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
index a2a4f33a3e3e..0075637f9b0b 100644
--- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
@@ -60,18 +60,6 @@
regulator-always-on;
};
- reg_5p0v_user_usb: regulator-5p0v-user-usb {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_user_usb>;
- vin-supply = <&reg_5p0v_main>;
- regulator-name = "5V_USER_USB";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
- startup-delay-us = <1000>;
- };
-
reg_3p3v_pmic: regulator-3p3v-pmic {
compatible = "regulator-fixed";
vin-supply = <&reg_12p0v>;
@@ -331,6 +319,39 @@
};
};
+&gpio3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio3_hog>;
+
+ usb-emulation {
+ gpio-hog;
+ gpios = <19 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "usb-emulation";
+ };
+
+ usb-mode1 {
+ gpio-hog;
+ gpios = <20 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb-mode1";
+ };
+
+ usb-pwr {
+ gpio-hog;
+ gpios = <22 GPIO_ACTIVE_LOW>;
+ output-high;
+ line-name = "usb-pwr-ctrl-en-n";
+ };
+
+ usb-mode2 {
+ gpio-hog;
+ gpios = <23 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb-mode2";
+ };
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
@@ -592,6 +613,16 @@
status = "disabled";
};
+ reg_5p0v_user_usb: charger@32 {
+ compatible = "microchip,ucs1002";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ucs1002_pins>;
+ reg = <0x32>;
+ interrupts-extended = <&gpio5 2 IRQ_TYPE_EDGE_BOTH>,
+ <&gpio3 21 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "a_det", "alert";
+ };
+
hpa1: amp@60 {
compatible = "ti,tpa6130a2";
pinctrl-names = "default";
@@ -629,7 +660,7 @@
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>;
cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ disable-wp;
vmmc-supply = <&reg_3p3v_sd>;
vqmmc-supply = <&reg_3p3v>;
no-1-8-v;
@@ -642,7 +673,7 @@
pinctrl-0 = <&pinctrl_usdhc3>;
bus-width = <4>;
cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+ disable-wp;
vmmc-supply = <&reg_3p3v_sd>;
vqmmc-supply = <&reg_3p3v>;
no-1-8-v;
@@ -776,6 +807,7 @@
&usbh1 {
vbus-supply = <&reg_5p0v_main>;
disable-over-current;
+ maximum-speed = "full-speed";
status = "okay";
};
@@ -936,6 +968,15 @@
>;
};
+ pinctrl_gpio3_hog: gpio3hoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
+ MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
+ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0
+ >;
+ };
+
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
@@ -983,12 +1024,6 @@
>;
};
- pinctrl_reg_user_usb: usbotggrp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x40000038
- >;
- };
-
pinctrl_rmii_phy_irq: phygrp {
fsl,pins = <
MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x40010000
@@ -1048,6 +1083,13 @@
>;
};
+ pinctrl_ucs1002_pins: ucs1002grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0
+ MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0
+ >;
+ };
+
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x10059
@@ -1056,7 +1098,6 @@
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
- MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x40010040
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x40010040
>;
};
@@ -1069,7 +1110,6 @@
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
- MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x40010040
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x40010040
>;
diff --git a/arch/arm/boot/dts/imx6sl-tolino-shine3.dts b/arch/arm/boot/dts/imx6sl-tolino-shine3.dts
new file mode 100644
index 000000000000..27143ea0f0f1
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl-tolino-shine3.dts
@@ -0,0 +1,322 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/*
+ * Device tree for the Tolino Shine 3 ebook reader
+ *
+ * Name on mainboard is: 37NB-E60K00+4A4
+ * Serials start with: E60K02 (a number also seen in
+ * vendor kernel sources)
+ *
+ * This mainboard seems to be equipped with different SoCs.
+ * In the Toline Shine 3 ebook reader it is a i.MX6SL
+ *
+ * Copyright 2019 Andreas Kemnade
+ * based on works
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6sl.dtsi"
+#include "e60k02.dtsi"
+
+/ {
+ model = "Tolino Shine 3";
+ compatible = "kobo,tolino-shine3", "fsl,imx6sl";
+};
+
+&gpio_keys {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+};
+
+&i2c1 {
+ pinctrl-names = "default","sleep";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_sleep>;
+};
+
+&i2c2 {
+ pinctrl-names = "default","sleep";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_sleep>;
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_gpio_keys: gpio-keysgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059 /* PWR_SW */
+ MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x17059 /* HALL_EN */
+ >;
+ };
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6SL_PAD_LCD_DAT0__GPIO2_IO20 0x79
+ MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x79
+ MX6SL_PAD_LCD_DAT2__GPIO2_IO22 0x79
+ MX6SL_PAD_LCD_DAT3__GPIO2_IO23 0x79
+ MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x79
+ MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x79
+ MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x79
+ MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x79
+ MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x79
+ MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x79
+ MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x79
+ MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x79
+ MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x79
+ MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x79
+ MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x79
+ MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x79
+ MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x79
+ MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x79
+ MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x79
+ MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x79
+ MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x79
+ MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x79
+ MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x79
+ MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x79
+ MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x79
+ MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x79
+ MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x79
+ MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x79
+ MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x79
+ MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x79
+ MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x79
+ MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79
+ MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x79
+ MX6SL_PAD_KEY_ROW6__GPIO4_IO05 0x79
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1
+ MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_i2c1_sleep: i2c1grp-sleep {
+ fsl,pins = <
+ MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1
+ MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1
+ MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_i2c2_sleep: i2c2grp-sleep {
+ fsl,pins = <
+ MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1
+ MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1
+ MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_led: ledgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x17059
+ >;
+ };
+
+ pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp {
+ fsl,pins = <
+ MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x10059 /* HWEN */
+ >;
+ };
+
+ pinctrl_ricoh_gpio: ricoh_gpiogrp {
+ fsl,pins = <
+ MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */
+ MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */
+ MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
+ MX6SL_PAD_UART1_RXD__UART1_TX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1grp {
+ fsl,pins = <
+ MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x13059
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc2_sleep: usdhc2grp-sleep {
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9
+ MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9
+ MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x100f9
+ MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x100f9
+ MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x100f9
+ MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x100f9
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc3_sleep: usdhc3grp-sleep {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1
+ MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1
+ MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1
+ MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1
+ MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1
+ MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1
+ >;
+ };
+
+ pinctrl_wifi_power: wifi-powergrp {
+ fsl,pins = <
+ MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */
+ >;
+ };
+
+ pinctrl_wifi_reset: wifi-resetgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */
+ >;
+ };
+};
+
+&leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led>;
+};
+
+&lm3630a {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>;
+};
+
+&reg_wifi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_power>;
+};
+
+&reg_vdd1p1 {
+ vin-supply = <&dcdc2_reg>;
+};
+
+&reg_vdd2p5 {
+ vin-supply = <&dcdc2_reg>;
+};
+
+&ricoh619 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ricoh_gpio>;
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc2_sleep>;
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc3_sleep>;
+};
+
+&wifi_pwrseq {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_reset>;
+};
diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
index 85aa8bb98528..a1bc5bb31756 100644
--- a/arch/arm/boot/dts/imx6sll.dtsi
+++ b/arch/arm/boot/dts/imx6sll.dtsi
@@ -632,6 +632,15 @@
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
};
+ pxp: pxp@20f0000 {
+ compatible = "fsl,imx6sll-pxp", "fsl,imx6ull-pxp";
+ reg = <0x20f0000 0x4000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_PXP>;
+ clock-names = "axi";
+ };
+
lcdif: lcd-controller@20f8000 {
compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif";
reg = <0x020f8000 0x4000>;
diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
index 91a7548fdb8d..dce5dcf96c25 100644
--- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
@@ -6,6 +6,7 @@
/ {
model = "Freescale i.MX6 SoloX SDB RevA Board";
+ compatible = "fsl,imx6sx-sdb-reva", "fsl,imx6sx";
};
&i2c1 {
diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
index 212144511b66..265bf4108cb6 100644
--- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
+++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
@@ -327,6 +327,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
no-1-8-v;
+ broken-cd;
keep-power-in-suspend;
wakeup-source;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index 6d850d997e1e..9145c536d71a 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -220,7 +220,7 @@
&iomuxc {
pinctrl_can_int: canint-grp {
fsl,pins = <
- MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0X14 /* SODIMM 73 */
+ MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */
>;
};
@@ -256,15 +256,15 @@
pinctrl_ecspi1_cs: ecspi1-cs-grp {
fsl,pins = <
- MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x000a0
+ MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x70a0 /* SODIMM 86 */
>;
};
pinctrl_ecspi1: ecspi1-grp {
fsl,pins = <
- MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0
- MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0
- MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0
+ MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 /* SODIMM 88 */
+ MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 /* SODIMM 92 */
+ MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0 /* SODIMM 90 */
>;
};
@@ -284,68 +284,68 @@
pinctrl_gpio_bl_on: gpio-bl-on-grp {
fsl,pins = <
- MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x000a0
+ MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x30a0 /* SODIMM 71 */
>;
};
pinctrl_gpio1: gpio1-grp {
fsl,pins = <
- MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0X14 /* SODIMM 77 */
- MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x14 /* SODIMM 99 */
- MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x14 /* SODIMM 133 */
- MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x14 /* SODIMM 135 */
- MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x14 /* SODIMM 100 */
- MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x14 /* SODIMM 102 */
- MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x14 /* SODIMM 104 */
- MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x14 /* SODIMM 186 */
+ MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x10b0 /* SODIMM 77 */
+ MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x70a0 /* SODIMM 99 */
+ MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x10b0 /* SODIMM 133 */
+ MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x10b0 /* SODIMM 135 */
+ MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x10b0 /* SODIMM 100 */
+ MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x70a0 /* SODIMM 102 */
+ MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x10b0 /* SODIMM 104 */
+ MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x10b0 /* SODIMM 186 */
>;
};
pinctrl_gpio2: gpio2-grp { /* Camera */
fsl,pins = <
- MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x74 /* SODIMM 69 */
- MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x14 /* SODIMM 75 */
- MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x14 /* SODIMM 85 */
- MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x14 /* SODIMM 96 */
- MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x14 /* SODIMM 98 */
+ MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x10b0 /* SODIMM 69 */
+ MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x10b0 /* SODIMM 75 */
+ MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x10b0 /* SODIMM 85 */
+ MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x10b0 /* SODIMM 96 */
+ MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 /* SODIMM 98 */
>;
};
pinctrl_gpio3: gpio3-grp { /* CAN2 */
fsl,pins = <
- MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x14 /* SODIMM 178 */
- MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x14 /* SODIMM 188 */
+ MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x10b0 /* SODIMM 178 */
+ MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x10b0 /* SODIMM 188 */
>;
};
pinctrl_gpio4: gpio4-grp {
fsl,pins = <
- MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x74 /* SODIMM 65 */
+ MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x10b0 /* SODIMM 65 */
>;
};
pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */
fsl,pins = <
- MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x74 /* SODIMM 106 */
+ MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */
>;
};
pinctrl_gpio6: gpio6-grp { /* Wifi pins */
fsl,pins = <
- MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x14 /* SODIMM 89 */
- MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x14 /* SODIMM 79 */
- MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x14 /* SODIMM 81 */
- MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x14 /* SODIMM 97 */
- MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x14 /* SODIMM 101 */
- MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x14 /* SODIMM 103 */
- MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x14 /* SODIMM 94 */
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10b0 /* SODIMM 89 */
+ MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 /* SODIMM 79 */
+ MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 /* SODIMM 81 */
+ MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x10b0 /* SODIMM 97 */
+ MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 /* SODIMM 101 */
+ MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 /* SODIMM 103 */
+ MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x10b0 /* SODIMM 94 */
>;
};
pinctrl_gpio7: gpio7-grp { /* CAN1 */
fsl,pins = <
- MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x74 /* SODIMM 55 */
- MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x74 /* SODIMM 63 */
+ MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0xb0b0/* SODIMM 55 */
+ MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */
>;
};
@@ -370,15 +370,15 @@
pinctrl_i2c1: i2c1-grp {
fsl,pins = <
- MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
- MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+ MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 /* SODIMM 196 */
+ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 /* SODIMM 194 */
>;
};
pinctrl_i2c1_gpio: i2c1-gpio-grp {
fsl,pins = <
- MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0
- MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0
+ MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 /* SODIMM 196 */
+ MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 /* SODIMM 194 */
>;
};
@@ -398,107 +398,107 @@
pinctrl_lcdif_dat: lcdif-dat-grp {
fsl,pins = <
- MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079
- MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079
- MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079
- MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079
- MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079
- MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079
- MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079
- MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079
- MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079
- MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079
- MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079
- MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079
- MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079
- MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079
- MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079
- MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079
- MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079
- MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079
+ MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 /* SODIMM 76 */
+ MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 /* SODIMM 70 */
+ MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079 /* SODIMM 60 */
+ MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079 /* SODIMM 58 */
+ MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079 /* SODIMM 78 */
+ MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079 /* SODIMM 72 */
+ MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079 /* SODIMM 80 */
+ MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079 /* SODIMM 46 */
+ MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079 /* SODIMM 62 */
+ MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079 /* SODIMM 48 */
+ MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079 /* SODIMM 74 */
+ MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079 /* SODIMM 50 */
+ MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079 /* SODIMM 52 */
+ MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079 /* SODIMM 54 */
+ MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079 /* SODIMM 66 */
+ MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079 /* SODIMM 64 */
+ MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079 /* SODIMM 57 */
+ MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079 /* SODIMM 61 */
>;
};
pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
fsl,pins = <
- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079
- MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079
- MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079
- MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079
+ MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 /* SODIMM 56 */
+ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 /* SODIMM 44 */
+ MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079 /* SODIMM 68 */
+ MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079 /* SODIMM 82 */
>;
};
pinctrl_pwm4: pwm4-grp {
fsl,pins = <
- MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079
+ MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 /* SODIMM 59 */
>;
};
pinctrl_pwm5: pwm5-grp {
fsl,pins = <
- MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079
+ MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 /* SODIMM 28 */
>;
};
pinctrl_pwm6: pwm6-grp {
fsl,pins = <
- MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079
+ MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 /* SODIMM 30 */
>;
};
pinctrl_pwm7: pwm7-grp {
fsl,pins = <
- MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079
+ MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 /* SODIMM 67 */
>;
};
pinctrl_uart1: uart1-grp {
fsl,pins = <
- MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1
- MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1
- MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1
- MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1
+ MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 /* SODIMM 33 */
+ MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 /* SODIMM 35 */
+ MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1 /* SODIMM 27 */
+ MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 /* SODIMM 25 */
>;
};
pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */
fsl,pins = <
- MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x1b0b1 /* DCD */
- MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x1b0b1 /* DSR */
- MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x1b0b1 /* DTR */
- MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x1b0b1 /* RI */
+ MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 */
+ MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 */
+ MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 */
+ MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 */
>;
};
pinctrl_uart2: uart2-grp {
fsl,pins = <
- MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
- MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
- MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1
- MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1
+ MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 /* SODIMM 36 */
+ MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 /* SODIMM 38 */
+ MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 /* SODIMM 32 */
+ MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 /* SODIMM 34 */
>;
};
pinctrl_uart5: uart5-grp {
fsl,pins = <
- MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1
- MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1
+ MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 /* SODIMM 19 */
+ MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 /* SODIMM 21 */
>;
};
pinctrl_usbh_reg: gpio-usbh-reg {
fsl,pins = <
- MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b0b1 /* SODIMM 129 USBH PEN */
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 */
>;
};
pinctrl_usdhc1: usdhc1-grp {
fsl,pins = <
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059
- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 /* SODIMM 47 */
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059 /* SODIMM 190 */
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 /* SODIMM 192 */
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 /* SODIMM 49 */
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 /* SODIMM 51 */
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 /* SODIMM 53 */
>;
};
@@ -533,7 +533,7 @@
MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059
MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17059
- MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x14
+ MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x10
>;
};
@@ -547,23 +547,23 @@
&iomuxc_snvs {
pinctrl_snvs_gpio1: snvs-gpio1-grp {
fsl,pins = <
- MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x14 /* SODIMM 93 */
- MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x14 /* SODIMM 95 */
- MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x74 /* SODIMM 105 */
- MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x14 /* SODIMM 131 USBH OC */
- MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x74 /* SODIMM 138 */
+ MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */
+ MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */
+ MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0a0 /* SODIMM 105 */
+ MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 */
+ MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */
>;
};
pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */
fsl,pins = <
- MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x74 /* SODIMM 107 */
+ MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */
>;
};
pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */
fsl,pins = <
- MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14 /* SODIMM 127 */
+ MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 /* SODIMM 127 */
>;
};
@@ -587,13 +587,13 @@
pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp {
fsl,pins = <
- MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130b0
+ MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 */
>;
};
pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp {
fsl,pins = <
- MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* CD */
+ MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 */
>;
};
@@ -605,7 +605,7 @@
pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp {
fsl,pins = <
- MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14
+ MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0
>;
};
};
diff --git a/arch/arm/boot/dts/imx7d-pico.dtsi b/arch/arm/boot/dts/imx7d-pico.dtsi
index 6f50ebf31a0a..e57da0d32b98 100644
--- a/arch/arm/boot/dts/imx7d-pico.dtsi
+++ b/arch/arm/boot/dts/imx7d-pico.dtsi
@@ -7,12 +7,42 @@
#include "imx7d.dtsi"
/ {
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm4 0 50000 0>;
+ brightness-levels = <0 36 72 108 144 180 216 255>;
+ default-brightness-level = <6>;
+ };
+
/* Will be filled by the bootloader */
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0>;
};
+ panel {
+ compatible = "vxt,vl050-8048nt-c01";
+ backlight = <&backlight>;
+ power-supply = <&reg_lcd_3v3>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
+ };
+
+ reg_lcd_3v3: regulator-lcd-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_lcdreg_on>;
+ regulator-name = "lcd-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
reg_wlreg_on: regulator-wlreg_on {
compatible = "regulator-fixed";
pinctrl-names = "default";
@@ -230,6 +260,18 @@
};
};
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdif>;
+ status = "okay";
+
+ port {
+ display_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+};
+
&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
@@ -260,6 +302,8 @@
};
&pwm4 { /* Backlight */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
@@ -413,6 +457,40 @@
>;
};
+ pinctrl_lcdif: lcdifgrp {
+ fsl,pins = <
+ MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
+ MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
+ MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
+ MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
+ MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
+ MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
+ MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
+ MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
+ MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
+ MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
+ MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
+ MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
+ MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
+ MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
+ MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
+ MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
+ MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
+ MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
+ MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
+ MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
+ MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
+ MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
+ MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
+ MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
+ MX7D_PAD_LCD_CLK__LCD_CLK 0x79
+ MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x78
+ MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x78
+ MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x78
+ MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14
+ >;
+ };
+
pinctrl_pwm1: pwm1 {
fsl,pins = <
MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x7f
@@ -431,6 +509,12 @@
>;
};
+ pinctrl_pwm4: pwm4grp{
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x7f
+ >;
+ };
+
pinctrl_reg_wlreg_on: regregongrp {
fsl,pins = <
MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59
@@ -577,6 +661,12 @@
>;
};
+ pinctrl_reg_lcdreg_on: reglcdongrp {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x59
+ >;
+ };
+
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
diff --git a/arch/arm/boot/dts/imx7d-sdb-reva.dts b/arch/arm/boot/dts/imx7d-sdb-reva.dts
index 7ce9d8c91985..cabdaa6dc518 100644
--- a/arch/arm/boot/dts/imx7d-sdb-reva.dts
+++ b/arch/arm/boot/dts/imx7d-sdb-reva.dts
@@ -7,6 +7,9 @@
#include "imx7d-sdb.dts"
/ {
+ model = "Freescale i.MX7 SabreSD RevA Board";
+ compatible = "fsl,imx7d-sdb-reva", "fsl,imx7d";
+
reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg_reva>;
gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index d8acd7cc7918..92f6d0c2a74f 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -12,7 +12,7 @@
clock-frequency = <996000000>;
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
- nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cells = <&fuse_grade>;
nvmem-cell-names = "speed_grade";
};
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index 1b812f4e7453..568d7a984aa6 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -152,8 +152,7 @@
interrupt-parent = <&gpc>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
fsl,tempmon = <&anatop>;
- nvmem-cells = <&tempmon_calib>,
- <&tempmon_temp_grade>;
+ nvmem-cells = <&tempmon_calib>, <&fuse_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
};
@@ -548,11 +547,7 @@
reg = <0x3c 0x4>;
};
- tempmon_temp_grade: temp-grade@10 {
- reg = <0x10 0x4>;
- };
-
- cpu_speed_grade: speed-grade@10 {
+ fuse_grade: fuse-grade@10 {
reg = <0x10 0x4>;
};
};
@@ -658,6 +653,12 @@
reg = <1>;
power-supply = <&reg_1p0d>;
};
+
+ pgc_hsic_phy: power-domain@2 {
+ #power-domain-cells = <0>;
+ reg = <2>;
+ power-supply = <&reg_1p2>;
+ };
};
};
};
@@ -1101,6 +1102,7 @@
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x30b30000 0x200>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pgc_hsic_phy>;
clocks = <&clks IMX7D_USB_CTRL_CLK>;
fsl,usbphy = <&usbphynop3>;
fsl,usbmisc = <&usbmisc3 0>;
diff --git a/arch/arm/boot/dts/imx7ulp-com.dts b/arch/arm/boot/dts/imx7ulp-com.dts
new file mode 100644
index 000000000000..d76fea3b35c6
--- /dev/null
+++ b/arch/arm/boot/dts/imx7ulp-com.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright 2019 NXP
+
+/dts-v1/;
+
+#include "imx7ulp.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Embedded Artists i.MX7ULP COM";
+ compatible = "ea,imx7ulp-com", "fsl,imx7ulp";
+
+ chosen {
+ stdout-path = &lpuart4;
+ };
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x4000000>;
+ };
+};
+
+&lpuart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart4>;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1_id>;
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ status = "okay";
+};
+
+&usdhc0 {
+ assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc0>;
+ non-removable;
+ bus-width = <8>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&iomuxc1 {
+ pinctrl_lpuart4: lpuart4grp {
+ fsl,pins = <
+ IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
+ IMX7ULP_PAD_PTC2__LPUART4_TX 0x3
+ >;
+ };
+
+ pinctrl_usbotg1_id: otg1idgrp {
+ fsl,pins = <
+ IMX7ULP_PAD_PTC13__USB0_ID 0x10003
+ >;
+ };
+
+ pinctrl_usdhc0: usdhc0grp {
+ fsl,pins = <
+ IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
+ IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042
+ IMX7ULP_PAD_PTD3__SDHC0_D7 0x43
+ IMX7ULP_PAD_PTD4__SDHC0_D6 0x43
+ IMX7ULP_PAD_PTD5__SDHC0_D5 0x43
+ IMX7ULP_PAD_PTD6__SDHC0_D4 0x43
+ IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
+ IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
+ IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
+ IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
+ IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
index ae75a1db3d9a..ebbe1518ef8a 100644
--- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
@@ -46,6 +46,49 @@
clock-frequency = <26000000>;
};
+ lcd_backlight: backlight {
+ compatible = "pwm-backlight";
+
+ pwms = <&pwm3 0 5000000 0>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ enable-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
+ };
+
+ lvds-receiver {
+ compatible = "ti,ds90cf384a", "lvds-decoder";
+ powerdown-gpios = <&gpio7 25 GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds_receiver_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ lvds_receiver_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
+
+ panel {
+ compatible = "edt,etm0700g0dh6";
+ backlight = <&lcd_backlight>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lvds_receiver_out>;
+ };
+ };
+ };
+
reg_1p5v: 1p5v {
compatible = "regulator-fixed";
regulator-name = "1P5V";
@@ -89,8 +132,7 @@
gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
};
@@ -120,6 +162,18 @@
status = "okay";
};
+&du {
+ status = "okay";
+};
+
+&gpio2 {
+ touch-interrupt {
+ gpio-hog;
+ gpios = <12 GPIO_ACTIVE_LOW>;
+ input;
+ };
+};
+
&hsusb {
status = "okay";
pinctrl-0 = <&usb0_pins>;
@@ -147,6 +201,25 @@
VDDIO-supply = <&reg_3p3v>;
VDDD-supply = <&reg_1p5v>;
};
+
+ touch: touchpanel@38 {
+ compatible = "edt,edt-ft5406";
+ reg = <0x38>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&lvds0 {
+ status = "okay";
+
+ ports {
+ port@1 {
+ lvds0_out: endpoint {
+ remote-endpoint = <&lvds_receiver_in>;
+ };
+ };
+ };
};
&pci0 {
@@ -180,6 +253,11 @@
function = "i2c2";
};
+ pwm3_pins: pwm3 {
+ groups = "pwm3";
+ function = "pwm3";
+ };
+
scif0_pins: scif0 {
groups = "scif0_data_d";
function = "scif0";
@@ -218,6 +296,12 @@
};
};
+&pwm3 {
+ pinctrl-0 = <&pwm3_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&rcar_sound {
pinctrl-0 = <&sound_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi b/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi
index 0e99df218252..ede2e0c999b1 100644
--- a/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi
+++ b/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi
@@ -39,7 +39,6 @@
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
- status = "okay";
ports {
port@0 {
diff --git a/arch/arm/boot/dts/ls1021a-tsn.dts b/arch/arm/boot/dts/ls1021a-tsn.dts
index 5b7689094b70..9d8f0c2a8aba 100644
--- a/arch/arm/boot/dts/ls1021a-tsn.dts
+++ b/arch/arm/boot/dts/ls1021a-tsn.dts
@@ -203,11 +203,15 @@
/* AR8031 */
sgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
+ /* SGMII1_PHY_INT_B: connected to IRQ2, active low */
+ interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
};
/* AR8031 */
sgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
+ /* SGMII2_PHY_INT_B: connected to IRQ2, active low */
+ interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
};
/* BCM5464 quad PHY */
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 2f6977ada447..0855b1fe98e0 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -216,6 +216,25 @@
compatible = "fsl,ls1021a-scfg", "syscon";
reg = <0x0 0x1570000 0x0 0x10000>;
big-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1570000 0x10000>;
+
+ extirq: interrupt-controller@1ac {
+ compatible = "fsl,ls1021a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1ac 4>;
+ interrupt-map =
+ <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xffffffff 0x0>;
+ };
};
crypto: crypto@1700000 {
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index c4447f6c8b2c..5d198309058a 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -282,4 +282,11 @@
};
};
};
+
+ xtal: xtal-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xtal";
+ #clock-cells = <0>;
+ };
}; /* end of / */
diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi
index 2d31b7ce3f8c..4716030a48d0 100644
--- a/arch/arm/boot/dts/meson6.dtsi
+++ b/arch/arm/boot/dts/meson6.dtsi
@@ -36,13 +36,6 @@
ranges = <0x0 0xd0000000 0x40000>;
};
- xtal: xtal-clk {
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "xtal";
- #clock-cells = <0>;
- };
-
clk81: clk@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 3c534cd50ee3..eedb92526968 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -3,6 +3,7 @@
* Copyright 2014 Carlo Caione <carlo@caione.org>
*/
+#include <dt-bindings/clock/meson8-ddr-clkc.h>
#include <dt-bindings/clock/meson8b-clkc.h>
#include <dt-bindings/gpio/meson8-gpio.h>
#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
@@ -129,8 +130,8 @@
gpu_opp_table: gpu-opp-table {
compatible = "operating-points-v2";
- opp-182150000 {
- opp-hz = /bits/ 64 <182150000>;
+ opp-182142857 {
+ opp-hz = /bits/ 64 <182142857>;
opp-microvolt = <1150000>;
};
opp-318750000 {
@@ -195,6 +196,14 @@
#size-cells = <1>;
ranges = <0x0 0xc8000000 0x8000>;
+ ddr_clkc: clock-controller@400 {
+ compatible = "amlogic,meson8-ddr-clkc";
+ reg = <0x400 0x20>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ #clock-cells = <1>;
+ };
+
dmcbus: bus@6000 {
compatible = "simple-bus";
reg = <0x6000 0x400>;
@@ -455,6 +464,8 @@
&hhi {
clkc: clock-controller {
compatible = "amlogic,meson8-clkc";
+ clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
+ clock-names = "xtal", "ddr_pll";
#clock-cells = <1>;
#reset-cells = <1>;
};
@@ -529,8 +540,7 @@
&saradc {
compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
- clocks = <&clkc CLKID_XTAL>,
- <&clkc CLKID_SAR_ADC>;
+ clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
clock-names = "clkin", "core";
amlogic,hhi-sysctrl = <&hhi>;
nvmem-cells = <&temperature_calib>;
@@ -548,31 +558,31 @@
};
&timer_abcde {
- clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
+ clocks = <&xtal>, <&clkc CLKID_CLK81>;
clock-names = "xtal", "pclk";
};
&uart_AO {
compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
+ clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>;
clock-names = "baud", "xtal", "pclk";
};
&uart_A {
compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
+ clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>;
clock-names = "baud", "xtal", "pclk";
};
&uart_B {
compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
+ clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>;
clock-names = "baud", "xtal", "pclk";
};
&uart_C {
compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
+ clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>;
clock-names = "baud", "xtal", "pclk";
};
diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts
index bed1dfef1985..163a200d5a7b 100644
--- a/arch/arm/boot/dts/meson8b-ec100.dts
+++ b/arch/arm/boot/dts/meson8b-ec100.dts
@@ -377,7 +377,7 @@
status = "okay";
pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
pinctrl-names = "default";
- clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>;
+ clocks = <&xtal>, <&xtal>;
clock-names = "clkin0", "clkin1";
};
diff --git a/arch/arm/boot/dts/meson8b-mxq.dts b/arch/arm/boot/dts/meson8b-mxq.dts
index 6e39ad52e42d..33037ef62d0a 100644
--- a/arch/arm/boot/dts/meson8b-mxq.dts
+++ b/arch/arm/boot/dts/meson8b-mxq.dts
@@ -165,7 +165,7 @@
status = "okay";
pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
pinctrl-names = "default";
- clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>;
+ clocks = <&xtal>, <&xtal>;
clock-names = "clkin0", "clkin1";
};
diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts
index a24eccc354b9..a2a47804fc4a 100644
--- a/arch/arm/boot/dts/meson8b-odroidc1.dts
+++ b/arch/arm/boot/dts/meson8b-odroidc1.dts
@@ -340,7 +340,7 @@
status = "okay";
pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
pinctrl-names = "default";
- clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>;
+ clocks = <&xtal>, <&xtal>;
clock-names = "clkin0", "clkin1";
};
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 099bf8e711c9..e34b039b9357 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -4,6 +4,7 @@
* Author: Carlo Caione <carlo@endlessm.com>
*/
+#include <dt-bindings/clock/meson8-ddr-clkc.h>
#include <dt-bindings/clock/meson8b-clkc.h>
#include <dt-bindings/gpio/meson8b-gpio.h>
#include <dt-bindings/reset/amlogic,meson8b-reset.h>
@@ -125,8 +126,8 @@
opp-hz = /bits/ 64 <255000000>;
opp-microvolt = <1100000>;
};
- opp-364300000 {
- opp-hz = /bits/ 64 <364300000>;
+ opp-364285714 {
+ opp-hz = /bits/ 64 <364285714>;
opp-microvolt = <1100000>;
};
opp-425000000 {
@@ -172,6 +173,14 @@
#size-cells = <1>;
ranges = <0x0 0xc8000000 0x8000>;
+ ddr_clkc: clock-controller@400 {
+ compatible = "amlogic,meson8b-ddr-clkc";
+ reg = <0x400 0x20>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ #clock-cells = <1>;
+ };
+
dmcbus: bus@6000 {
compatible = "simple-bus";
reg = <0x6000 0x400>;
@@ -433,7 +442,9 @@
&hhi {
clkc: clock-controller {
- compatible = "amlogic,meson8-clkc";
+ compatible = "amlogic,meson8b-clkc";
+ clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
+ clock-names = "xtal", "ddr_pll";
#clock-cells = <1>;
#reset-cells = <1>;
};
@@ -508,8 +519,7 @@
&saradc {
compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
- clocks = <&clkc CLKID_XTAL>,
- <&clkc CLKID_SAR_ADC>;
+ clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
clock-names = "clkin", "core";
amlogic,hhi-sysctrl = <&hhi>;
nvmem-cells = <&temperature_calib>;
@@ -523,31 +533,31 @@
};
&timer_abcde {
- clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
+ clocks = <&xtal>, <&clkc CLKID_CLK81>;
clock-names = "xtal", "pclk";
};
&uart_AO {
compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
+ clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>;
clock-names = "baud", "xtal", "pclk";
};
&uart_A {
compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
+ clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>;
clock-names = "baud", "xtal", "pclk";
};
&uart_B {
compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
+ clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>;
clock-names = "baud", "xtal", "pclk";
};
&uart_C {
compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
+ clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>;
clock-names = "baud", "xtal", "pclk";
};
diff --git a/arch/arm/boot/dts/mmp3-dell-ariel.dts b/arch/arm/boot/dts/mmp3-dell-ariel.dts
index c1947b5a688d..15449c72c042 100644
--- a/arch/arm/boot/dts/mmp3-dell-ariel.dts
+++ b/arch/arm/boot/dts/mmp3-dell-ariel.dts
@@ -49,6 +49,28 @@
status = "okay";
};
+&hsic0 {
+ status = "okay";
+
+ usb1@1 {
+ compatible = "usb424,2640";
+ reg = <0x01>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+
+ mass-storage@1 {
+ compatible = "usb424,4040";
+ reg = <0x01>;
+ status = "disabled";
+ };
+ };
+};
+
+&hsic_phy0 {
+ status = "okay";
+ reset-gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
+};
+
&mmc3 {
status = "okay";
max-frequency = <50000000>;
diff --git a/arch/arm/boot/dts/mmp3.dtsi b/arch/arm/boot/dts/mmp3.dtsi
index 6f480827b94d..59a108e49b41 100644
--- a/arch/arm/boot/dts/mmp3.dtsi
+++ b/arch/arm/boot/dts/mmp3.dtsi
@@ -201,6 +201,50 @@
status = "disabled";
};
+ hsic_phy0: hsic-phy@f0001800 {
+ compatible = "marvell,mmp3-hsic-phy",
+ "usb-nop-xceiv";
+ reg = <0xf0001800 0x40>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ hsic0: hsic@f0001000 {
+ compatible = "marvell,pxau2o-ehci";
+ reg = <0xf0001000 0x200>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clocks MMP2_CLK_USBHSIC0>;
+ clock-names = "USBCLK";
+ phys = <&hsic_phy0>;
+ phy-names = "usb";
+ phy_type = "hsic";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "disabled";
+ };
+
+ hsic_phy1: hsic-phy@f0002800 {
+ compatible = "marvell,mmp3-hsic-phy",
+ "usb-nop-xceiv";
+ reg = <0xf0002800 0x40>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ hsic1: hsic@f0002000 {
+ compatible = "marvell,pxau2o-ehci";
+ reg = <0xf0002000 0x200>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clocks MMP2_CLK_USBHSIC1>;
+ clock-names = "USBCLK";
+ phys = <&hsic_phy1>;
+ phy-names = "usb";
+ phy_type = "hsic";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "disabled";
+ };
+
mmc1: mmc@d4280000 {
compatible = "mrvl,pxav3-mmc";
reg = <0xd4280000 0x120>;
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 000bf16de651..0e453fec2e3a 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -8,6 +8,7 @@
* kind, whether express or implied.
*/
+#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/omap.h>
@@ -79,17 +80,37 @@
reg = <0x480FE000 0x1000>;
};
- sdma: dma-controller@48056000 {
- compatible = "ti,omap2430-sdma", "ti,omap2420-sdma";
- ti,hwmods = "dma";
- reg = <0x48056000 0x1000>;
- interrupts = <12>,
- <13>,
- <14>,
- <15>;
- #dma-cells = <1>;
- dma-channels = <32>;
- dma-requests = <64>;
+ target-module@48056000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x48056000 0x4>,
+ <0x4805602c 0x4>,
+ <0x48056028 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ clocks = <&core_l3_ck>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x48056000 0x1000>;
+
+ sdma: dma-controller@0 {
+ compatible = "ti,omap2420-sdma", "ti,omap-sdma";
+ reg = <0 0x1000>;
+ interrupts = <12>,
+ <13>,
+ <14>,
+ <15>;
+ #dma-cells = <1>;
+ dma-channels = <32>;
+ dma-requests = <64>;
+ };
};
i2c1: i2c@48070000 {
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 7f57af2f10ac..15ef7593be12 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -309,6 +309,10 @@
};
};
+&sdma {
+ compatible = "ti,omap2430-sdma", "ti,omap-sdma";
+};
+
&i2c1 {
compatible = "ti,omap2430-i2c";
};
diff --git a/arch/arm/boot/dts/omap3-echo.dts b/arch/arm/boot/dts/omap3-echo.dts
new file mode 100644
index 000000000000..93ffeddada1e
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-echo.dts
@@ -0,0 +1,461 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2019 André Hentschel <nerv@dawncrow.de>
+ */
+/dts-v1/;
+
+#include "dm3725.dtsi"
+
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Amazon Echo (first generation)";
+ compatible = "amazon,omap3-echo", "ti,omap3630", "ti,omap3";
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = <&vdd1_reg>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0xc600000>; /* 198 MB */
+ };
+
+ vcc5v: fixedregulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vcc3v3: fixedregulator1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vcc1v8: fixedregulator2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <40>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&button_pins>;
+
+ mute-button {
+ label = "mute";
+ linux,code = <KEY_MUTE>;
+ gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; /* GPIO_70 */
+ wakeup-source;
+ };
+
+ help-button {
+ label = "help";
+ linux,code = <KEY_HELP>;
+ gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; /* GPIO_72 */
+ wakeup-source;
+ };
+ };
+
+ rotary: rotary-encoder {
+ compatible = "rotary-encoder";
+ gpios = <
+ &gpio3 5 GPIO_ACTIVE_HIGH /* GPIO_69 */
+ &gpio3 12 GPIO_ACTIVE_HIGH /* GPIO_76 */
+ >;
+ linux,axis = <REL_X>;
+ rotary-encoder,relative-axis;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+
+ tps: tps@2d {
+ reg = <0x2d>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+
+ lp5523A: lp5523A@32 {
+ compatible = "national,lp5523";
+ label = "q1";
+ reg = <0x32>;
+ clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */
+ enable-gpio = <&gpio4 13 GPIO_ACTIVE_HIGH>; /* GPIO_109 */
+
+ chan0 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan1 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan2 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan3 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan4 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan5 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan6 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan7 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan8 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ };
+
+ lp5523B: lp5523B@33 {
+ compatible = "national,lp5523";
+ label = "q3";
+ reg = <0x33>;
+ clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */
+
+ chan0 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan1 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan2 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan3 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan4 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan5 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan6 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan7 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan8 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ };
+
+ lp5523C: lp5523C@34 {
+ compatible = "national,lp5523";
+ label = "q4";
+ reg = <0x34>;
+ clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */
+
+ chan0 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan1 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan2 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan3 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan4 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan5 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan6 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan7 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan8 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ };
+
+ lp5523D: lp552D@35 {
+ compatible = "national,lp5523";
+ label = "q2";
+ reg = <0x35>;
+ clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */
+
+ chan0 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan1 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan2 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan3 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan4 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan5 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan6 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan7 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan8 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ };
+};
+
+#include "tps65910.dtsi"
+
+&omap3_pmx_core {
+ tps_pins: pinmux_tps_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | PIN_OFF_INPUT_PULLUP | PIN_OFF_OUTPUT_LOW | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* sys_nirq.sys_nirq */
+ >;
+ };
+
+ button_pins: pinmux_button_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x20dc, PIN_INPUT | MUX_MODE4) /* dss_data0.gpio_70 */
+ OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* dss_data2.gpio_72 */
+ >;
+ };
+
+ mmc1_pins: pinmux_mmc1_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
+ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
+ OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
+ OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
+ OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
+ OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
+ >;
+ };
+
+ mmc2_pins: pinmux_mmc2_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
+ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
+ OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
+ OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
+ OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
+ OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
+ OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4.sdmmc2_dat4 */
+ OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5.sdmmc2_dat5 */
+ OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6.sdmmc2_dat6 */
+ OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7.sdmmc2_dat7 */
+ >;
+ };
+};
+
+&omap3_pmx_core2 {
+ mmc3_pins: pinmux_mmc3_pins {
+ pinctrl-single,pins = <
+ OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */
+ OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */
+ OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */
+ OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */
+ OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */
+ OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */
+ >;
+ };
+};
+
+&mmc1 {
+ status = "okay";
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ vmmc-supply = <&vmmc_reg>;
+};
+
+&mmc2 {
+ status = "okay";
+ bus-width = <8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ vmmc-supply = <&vmmc_reg>;
+};
+
+&mmc3 {
+ status = "okay";
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_pins>;
+ non-removable;
+ disable-wp;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ vmmc-supply = <&vcc3v3>;
+ vqmmc-supply = <&vcc1v8>;
+};
+
+&tps {
+ pinctrl-names = "default";
+ pinctrl-0 = <&tps_pins>;
+
+ interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+ interrupt-parent = <&intc>;
+
+ ti,en-ck32k-xtal;
+ ti,system-power-controller;
+
+ vcc1-supply = <&vcc5v>;
+ vcc2-supply = <&vcc5v>;
+ vcc3-supply = <&vcc5v>;
+ vcc4-supply = <&vcc5v>;
+ vcc5-supply = <&vcc5v>;
+ vcc6-supply = <&vcc5v>;
+ vcc7-supply = <&vcc5v>;
+ vccio-supply = <&vcc5v>;
+
+ regulators {
+
+ vio_reg: regulator@1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ vdd1_reg: regulator@2 {
+ regulator-name = "vdd_mpu";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd2_reg: regulator@3 {
+ regulator-name = "vdd_dsp";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ };
+
+ vdd3_reg: regulator@4 {
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vdig1_reg: regulator@5 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <2700000>;
+ regulator-always-on;
+ };
+
+ vdig2_reg: regulator@6 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ vpll_reg: regulator@7 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ vdac_reg: regulator@8 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vaux1_reg: regulator@9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ vaux2_reg: regulator@10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vaux33_reg: regulator@11 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vmmc_reg: regulator@12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index a638e059135b..c3c6d7d04a76 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -482,6 +482,11 @@
regulator-always-on;
};
+/* First two dma channels are reserved on secure omap3 */
+&sdma {
+ dma-channel-mask = <0xfffffffc>;
+};
+
&twl {
twl_audio: audio {
compatible = "ti,twl4030-audio";
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 5698a3e241aa..634ea16a711e 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -206,17 +206,41 @@
reg = <0x48200000 0x1000>;
};
- sdma: dma-controller@48056000 {
- compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
- reg = <0x48056000 0x1000>;
- interrupts = <12>,
- <13>,
- <14>,
- <15>;
- #dma-cells = <1>;
- dma-channels = <32>;
- dma-requests = <96>;
- ti,hwmods = "dma";
+ target-module@48056000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x48056000 0x4>,
+ <0x4805602c 0x4>,
+ <0x48056028 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, core_l3_clkdm */
+ clocks = <&core_l3_ick>;
+ clock-names = "ick";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x48056000 0x1000>;
+
+ sdma: dma-controller@0 {
+ compatible = "ti,omap3430-sdma", "ti,omap-sdma";
+ reg = <0x0 0x1000>;
+ interrupts = <12>,
+ <13>,
+ <14>,
+ <15>;
+ #dma-cells = <1>;
+ dma-channels = <32>;
+ dma-requests = <96>;
+ };
};
gpio1: gpio@48310000 {
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index c618cb257d00..71f3c8f1f924 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -223,6 +223,10 @@
};
};
+&sdma {
+ compatible = "ti,omap3630-sdma", "ti,omap-sdma";
+};
+
/* OMAP3630 needs dss_96m_fck for VENC */
&venc {
clocks = <&dss_tv_fck>, <&dss_96m_fck>;
diff --git a/arch/arm/boot/dts/omap4-l4-abe.dtsi b/arch/arm/boot/dts/omap4-l4-abe.dtsi
index 6c892fc9d726..a6feb201c569 100644
--- a/arch/arm/boot/dts/omap4-l4-abe.dtsi
+++ b/arch/arm/boot/dts/omap4-l4-abe.dtsi
@@ -219,7 +219,6 @@
target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "dmic";
reg = <0x2e000 0x4>,
<0x2e010 0x4>;
reg-names = "rev", "sysc";
@@ -279,7 +278,6 @@
mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mcpdm";
reg = <0x32000 0x4>,
<0x32010 0x4>;
reg-names = "rev", "sysc";
@@ -314,7 +312,6 @@
target-module@38000 { /* 0x40138000, ap 18 12.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer5";
reg = <0x38000 0x4>,
<0x38010 0x4>;
reg-names = "rev", "sysc";
@@ -345,7 +342,6 @@
target-module@3a000 { /* 0x4013a000, ap 20 14.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer6";
reg = <0x3a000 0x4>,
<0x3a010 0x4>;
reg-names = "rev", "sysc";
@@ -376,7 +372,6 @@
target-module@3c000 { /* 0x4013c000, ap 22 16.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer7";
reg = <0x3c000 0x4>,
<0x3c010 0x4>;
reg-names = "rev", "sysc";
@@ -407,7 +402,6 @@
target-module@3e000 { /* 0x4013e000, ap 24 18.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer8";
reg = <0x3e000 0x4>,
<0x3e010 0x4>;
reg-names = "rev", "sysc";
@@ -466,7 +460,6 @@
target-module@f1000 { /* 0x401f1000, ap 32 20.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "aess";
reg = <0xf1000 0x4>,
<0xf1010 0x4>;
reg-names = "rev", "sysc";
diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi
index 83f803be8ee2..408f51cbfbb3 100644
--- a/arch/arm/boot/dts/omap4-l4.dtsi
+++ b/arch/arm/boot/dts/omap4-l4.dtsi
@@ -136,7 +136,6 @@
target-module@56000 { /* 0x4a056000, ap 7 0a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "dma_system";
reg = <0x56000 0x4>,
<0x5602c 0x4>,
<0x56028 0x4>;
@@ -160,7 +159,7 @@
ranges = <0x0 0x56000 0x1000>;
sdma: dma-controller@0 {
- compatible = "ti,omap4430-sdma";
+ compatible = "ti,omap4430-sdma", "ti,omap-sdma";
reg = <0x0 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
@@ -174,7 +173,6 @@
target-module@58000 { /* 0x4a058000, ap 10 0e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "hsi";
reg = <0x58000 0x4>,
<0x58010 0x4>,
<0x58014 0x4>;
@@ -321,7 +319,6 @@
target-module@66000 { /* 0x4a066000, ap 25 26.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "mmu_dsp";
reg = <0x66000 0x4>,
<0x66010 0x4>,
<0x66014 0x4>;
@@ -335,12 +332,18 @@
/* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */
clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
clock-names = "fck";
+ resets = <&prm_tesla 1>;
+ reset-names = "rstctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x66000 0x1000>;
- /* mmu_dsp cannot be moved before reset driver */
- status = "disabled";
+ mmu_dsp: mmu@0 {
+ compatible = "ti,omap4-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ };
};
};
@@ -420,7 +423,6 @@
target-module@2d000 { /* 0x4a0ad000, ap 88 0c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "ocp2scp_usb_phy";
reg = <0x2d000 0x4>,
<0x2d010 0x4>,
<0x2d014 0x4>;
@@ -499,7 +501,6 @@
target-module@59000 { /* 0x4a0d9000, ap 13 1a.0 */
compatible = "ti,sysc-omap4-sr", "ti,sysc";
- ti,hwmods = "smartreflex_mpu";
reg = <0x59038 0x4>;
reg-names = "sysc";
ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
@@ -523,7 +524,6 @@
target-module@5b000 { /* 0x4a0db000, ap 15 08.0 */
compatible = "ti,sysc-omap4-sr", "ti,sysc";
- ti,hwmods = "smartreflex_iva";
reg = <0x5b038 0x4>;
reg-names = "sysc";
ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
@@ -547,7 +547,6 @@
target-module@5d000 { /* 0x4a0dd000, ap 17 22.0 */
compatible = "ti,sysc-omap4-sr", "ti,sysc";
- ti,hwmods = "smartreflex_core";
reg = <0x5d038 0x4>;
reg-names = "sysc";
ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
@@ -613,7 +612,6 @@
target-module@76000 { /* 0x4a0f6000, ap 29 3a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "spinlock";
reg = <0x76000 0x4>,
<0x76010 0x4>,
<0x76014 0x4>;
@@ -721,7 +719,6 @@
target-module@a000 { /* 0x4a10a000, ap 65 50.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "fdif";
reg = <0xa000 0x4>,
<0xa010 0x4>;
reg-names = "rev", "sysc";
@@ -1177,7 +1174,6 @@
target-module@c000 { /* 0x4a31c000, ap 11 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "kbd";
reg = <0xc000 0x4>,
<0xc010 0x4>,
<0xc014 0x4>;
@@ -1422,7 +1418,6 @@
target-module@32000 { /* 0x48032000, ap 5 02.0 */
compatible = "ti,sysc-omap2-timer", "ti,sysc";
- ti,hwmods = "timer2";
reg = <0x32000 0x4>,
<0x32010 0x4>,
<0x32014 0x4>;
@@ -1454,7 +1449,6 @@
target-module@34000 { /* 0x48034000, ap 7 04.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer3";
reg = <0x34000 0x4>,
<0x34010 0x4>;
reg-names = "rev", "sysc";
@@ -1482,7 +1476,6 @@
target-module@36000 { /* 0x48036000, ap 9 0e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer4";
reg = <0x36000 0x4>,
<0x36010 0x4>;
reg-names = "rev", "sysc";
@@ -1510,7 +1503,6 @@
target-module@3e000 { /* 0x4803e000, ap 11 08.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer9";
reg = <0x3e000 0x4>,
<0x3e010 0x4>;
reg-names = "rev", "sysc";
@@ -1892,7 +1884,6 @@
target-module@76000 { /* 0x48076000, ap 39 38.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "slimbus2";
reg = <0x76000 0x4>,
<0x76010 0x4>;
reg-names = "rev", "sysc";
@@ -1913,7 +1904,6 @@
target-module@78000 { /* 0x48078000, ap 41 1a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "elm";
reg = <0x78000 0x4>,
<0x78010 0x4>,
<0x78014 0x4>;
@@ -1942,7 +1932,6 @@
target-module@86000 { /* 0x48086000, ap 43 24.0 */
compatible = "ti,sysc-omap2-timer", "ti,sysc";
- ti,hwmods = "timer10";
reg = <0x86000 0x4>,
<0x86010 0x4>,
<0x86014 0x4>;
@@ -1975,7 +1964,6 @@
target-module@88000 { /* 0x48088000, ap 45 2e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer11";
reg = <0x88000 0x4>,
<0x88010 0x4>;
reg-names = "rev", "sysc";
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 2de8a6b53de9..38b4146d4d33 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -173,14 +173,6 @@
#gpio-cells = <2>;
};
- mmu_dsp: mmu@4a066000 {
- compatible = "ti,omap4-iommu";
- reg = <0x4a066000 0x100>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu_dsp";
- #iommu-cells = <0>;
- };
-
target-module@52000000 {
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "iss";
@@ -206,17 +198,37 @@
/* No child device binding, driver in staging */
};
- mmu_ipu: mmu@55082000 {
- compatible = "ti,omap4-iommu";
- reg = <0x55082000 0x100>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu_ipu";
- #iommu-cells = <0>;
- ti,iommu-bus-err-back;
+ target-module@55082000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x55082000 0x4>,
+ <0x55082010 0x4>,
+ <0x55082014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_core 2>;
+ reset-names = "rstctrl";
+ ranges = <0x0 0x55082000 0x100>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+
+ mmu_ipu: mmu@0 {
+ compatible = "ti,omap4-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,iommu-bus-err-back;
+ };
};
+
target-module@4012c000 {
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "slimbus1";
reg = <0x4012c000 0x4>,
<0x4012c010 0x4>;
reg-names = "rev", "sysc";
diff --git a/arch/arm/boot/dts/omap5-l4-abe.dtsi b/arch/arm/boot/dts/omap5-l4-abe.dtsi
index 23aa90716f7f..4ec7909df78b 100644
--- a/arch/arm/boot/dts/omap5-l4-abe.dtsi
+++ b/arch/arm/boot/dts/omap5-l4-abe.dtsi
@@ -203,7 +203,6 @@
target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "dmic";
reg = <0x2e000 0x4>,
<0x2e010 0x4>;
reg-names = "rev", "sysc";
@@ -244,7 +243,6 @@
mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mcpdm";
reg = <0x32000 0x4>,
<0x32010 0x4>;
reg-names = "rev", "sysc";
@@ -279,7 +277,6 @@
target-module@38000 { /* 0x40138000, ap 18 12.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer5";
reg = <0x38000 0x4>,
<0x38010 0x4>;
reg-names = "rev", "sysc";
@@ -311,7 +308,6 @@
target-module@3a000 { /* 0x4013a000, ap 20 14.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer6";
reg = <0x3a000 0x4>,
<0x3a010 0x4>;
reg-names = "rev", "sysc";
@@ -343,7 +339,6 @@
target-module@3c000 { /* 0x4013c000, ap 22 16.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer7";
reg = <0x3c000 0x4>,
<0x3c010 0x4>;
reg-names = "rev", "sysc";
@@ -374,7 +369,6 @@
target-module@3e000 { /* 0x4013e000, ap 24 18.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer8";
reg = <0x3e000 0x4>,
<0x3e010 0x4>;
reg-names = "rev", "sysc";
diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi
index 25aacf1ba708..34410b7d77e2 100644
--- a/arch/arm/boot/dts/omap5-l4.dtsi
+++ b/arch/arm/boot/dts/omap5-l4.dtsi
@@ -213,7 +213,6 @@
target-module@56000 { /* 0x4a056000, ap 7 02.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "dma_system";
reg = <0x56000 0x4>,
<0x5602c 0x4>,
<0x56028 0x4>;
@@ -237,7 +236,7 @@
ranges = <0x0 0x56000 0x1000>;
sdma: dma-controller@0 {
- compatible = "ti,omap4430-sdma";
+ compatible = "ti,omap4430-sdma", "ti,omap-sdma";
reg = <0x0 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
@@ -349,7 +348,6 @@
target-module@66000 { /* 0x4a066000, ap 23 0a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "mmu_dsp";
reg = <0x66000 0x4>,
<0x66010 0x4>,
<0x66014 0x4>;
@@ -364,12 +362,18 @@
/* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */
clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
clock-names = "fck";
+ resets = <&prm_dsp 1>;
+ reset-names = "rstctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x66000 0x1000>;
- /* mmu_dsp cannot be moved before reset driver */
- status = "disabled";
+ mmu_dsp: mmu@0 {
+ compatible = "ti,omap4-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ };
};
target-module@70000 { /* 0x4a070000, ap 79 2e.0 */
@@ -430,7 +434,6 @@
target-module@0 { /* 0x4a080000, ap 83 28.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "ocp2scp1";
reg = <0x0 0x4>,
<0x10 0x4>,
<0x14 0x4>;
@@ -488,7 +491,6 @@
target-module@10000 { /* 0x4a090000, ap 89 36.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "ocp2scp3";
reg = <0x10000 0x4>,
<0x10010 0x4>,
<0x10014 0x4>;
@@ -627,7 +629,6 @@
target-module@76000 { /* 0x4a0f6000, ap 27 0c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "spinlock";
reg = <0x76000 0x4>,
<0x76010 0x4>,
<0x76014 0x4>;
@@ -1061,7 +1062,6 @@
target-module@32000 { /* 0x48032000, ap 5 3e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer2";
reg = <0x32000 0x4>,
<0x32010 0x4>;
reg-names = "rev", "sysc";
@@ -1089,7 +1089,6 @@
target-module@34000 { /* 0x48034000, ap 7 46.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer3";
reg = <0x34000 0x4>,
<0x34010 0x4>;
reg-names = "rev", "sysc";
@@ -1117,7 +1116,6 @@
target-module@36000 { /* 0x48036000, ap 9 4e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer4";
reg = <0x36000 0x4>,
<0x36010 0x4>;
reg-names = "rev", "sysc";
@@ -1145,7 +1143,6 @@
target-module@3e000 { /* 0x4803e000, ap 11 56.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer9";
reg = <0x3e000 0x4>,
<0x3e010 0x4>;
reg-names = "rev", "sysc";
@@ -1713,7 +1710,6 @@
target-module@86000 { /* 0x48086000, ap 41 5e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer10";
reg = <0x86000 0x4>,
<0x86010 0x4>;
reg-names = "rev", "sysc";
@@ -1742,7 +1738,6 @@
target-module@88000 { /* 0x48088000, ap 43 66.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer11";
reg = <0x88000 0x4>,
<0x88010 0x4>;
reg-names = "rev", "sysc";
@@ -2358,7 +2353,6 @@
target-module@c000 { /* 0x4ae1c000, ap 11 1c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "kbd";
reg = <0xc000 0x4>,
<0xc010 0x4>;
reg-names = "rev", "sysc";
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 1f6ad1debc90..d0ecf54d5a23 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -186,21 +186,33 @@
#gpio-cells = <2>;
};
- mmu_dsp: mmu@4a066000 {
- compatible = "ti,omap4-iommu";
- reg = <0x4a066000 0x100>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu_dsp";
- #iommu-cells = <0>;
- };
+ target-module@55082000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x55082000 0x4>,
+ <0x55082010 0x4>,
+ <0x55082014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_core 2>;
+ reset-names = "rstctrl";
+ ranges = <0x0 0x55082000 0x100>;
+ #size-cells = <1>;
+ #address-cells = <1>;
- mmu_ipu: mmu@55082000 {
- compatible = "ti,omap4-iommu";
- reg = <0x55082000 0x100>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu_ipu";
- #iommu-cells = <0>;
- ti,iommu-bus-err-back;
+ mmu_ipu: mmu@0 {
+ compatible = "ti,omap4-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,iommu-bus-err-back;
+ };
};
dmm@4e000000 {
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index 0a0fb147ebb9..fa1852eed37b 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
+#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-apq8084.h>
#include <dt-bindings/gpio/gpio.h>
@@ -184,7 +185,7 @@
cpu-pmu {
compatible = "qcom,krait-pmu";
- interrupts = <1 7 0xf04>;
+ interrupts = <GIC_PPI 7 0xf04>;
};
clocks {
@@ -203,10 +204,10 @@
timer {
compatible = "arm,armv7-timer";
- interrupts = <1 2 0xf08>,
- <1 3 0xf08>,
- <1 4 0xf08>,
- <1 1 0xf08>;
+ interrupts = <GIC_PPI 2 0xf08>,
+ <GIC_PPI 3 0xf08>,
+ <GIC_PPI 4 0xf08>,
+ <GIC_PPI 1 0xf08>;
clock-frequency = <19200000>;
};
@@ -253,12 +254,13 @@
tsens: thermal-sensor@fc4a8000 {
compatible = "qcom,msm8974-tsens";
- reg = <0xfc4a8000 0x2000>;
+ reg = <0xfc4a9000 0x1000>, /* TM */
+ <0xfc4a8000 0x1000>; /* SROT */
nvmem-cells = <&tsens_calib>, <&tsens_backup>;
nvmem-cell-names = "calib", "calib_backup";
+ #qcom,sensors = <11>;
#thermal-sensor-cells = <1>;
};
-
timer@f9020000 {
#address-cells = <1>;
#size-cells = <1>;
@@ -269,50 +271,50 @@
frame@f9021000 {
frame-number = <0>;
- interrupts = <0 8 0x4>,
- <0 7 0x4>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9021000 0x1000>,
<0xf9022000 0x1000>;
};
frame@f9023000 {
frame-number = <1>;
- interrupts = <0 9 0x4>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9023000 0x1000>;
status = "disabled";
};
frame@f9024000 {
frame-number = <2>;
- interrupts = <0 10 0x4>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9024000 0x1000>;
status = "disabled";
};
frame@f9025000 {
frame-number = <3>;
- interrupts = <0 11 0x4>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9025000 0x1000>;
status = "disabled";
};
frame@f9026000 {
frame-number = <4>;
- interrupts = <0 12 0x4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9026000 0x1000>;
status = "disabled";
};
frame@f9027000 {
frame-number = <5>;
- interrupts = <0 13 0x4>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9027000 0x1000>;
status = "disabled";
};
frame@f9028000 {
frame-number = <6>;
- interrupts = <0 14 0x4>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9028000 0x1000>;
status = "disabled";
};
@@ -404,13 +406,13 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
- interrupts = <0 208 0>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
};
blsp2_uart2: serial@f995e000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf995e000 0x1000>;
- interrupts = <0 114 0x0>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
@@ -420,7 +422,7 @@
compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
reg-names = "hc_mem", "core_mem";
- interrupts = <0 123 0>, <0 138 0>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>,
@@ -433,7 +435,7 @@
compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
reg-names = "hc_mem", "core_mem";
- interrupts = <0 125 0>, <0 221 0>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
<&gcc GCC_SDCC2_AHB_CLK>,
@@ -449,7 +451,7 @@
<0xfc4cb000 0x1000>,
<0xfc4ca000 0x1000>;
interrupt-names = "periph_irq";
- interrupts = <0 190 0>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
@@ -463,7 +465,7 @@
compatible = "qcom,smd";
rpm {
- interrupts = <0 168 1>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 8ef26da32ff4..71bb25a8afc0 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -102,6 +102,7 @@
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
+ qcom,saw = <&saw_l2>;
};
};
@@ -353,6 +354,12 @@
regulator;
};
+ saw_l2: regulator@b012000 {
+ compatible = "qcom,saw2";
+ reg = <0xb012000 0x1000>;
+ regulator;
+ };
+
blsp1_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
diff --git a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts
index 26160394d717..d2d48770ec0f 100644
--- a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts
+++ b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts
@@ -259,6 +259,25 @@
status = "ok";
};
+ remoteproc@fb21b000 {
+ status = "ok";
+
+ vddmx-supply = <&pm8841_s1>;
+ vddcx-supply = <&pm8841_s2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wcnss_pin_a>;
+
+ smd-edge {
+ qcom,remote-pid = <4>;
+ label = "pronto";
+
+ wcnss {
+ status = "ok";
+ };
+ };
+ };
+
pinctrl@fd510000 {
sdhc1_pin_a: sdhc1-pin-active {
clk {
@@ -287,6 +306,32 @@
bias-pull-up;
};
};
+
+ wcnss_pin_a: wcnss-pin-active {
+ wlan {
+ pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40";
+ function = "wlan";
+
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+
+ bt {
+ pins = "gpio35", "gpio43", "gpio44";
+ function = "bt";
+
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ fm {
+ pins = "gpio41", "gpio42";
+ function = "fm";
+
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
};
sdhci@f9824900 {
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 9a84eb0cbbe6..4b161b809dd5 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
+#include <dt-bindings/interconnect/qcom,msm8974.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
@@ -20,17 +21,17 @@
#size-cells = <1>;
ranges;
- mpss@8000000 {
+ mpss_region: mpss@8000000 {
reg = <0x08000000 0x5100000>;
no-map;
};
- mba@d100000 {
+ mba_region: mba@d100000 {
reg = <0x0d100000 0x100000>;
no-map;
};
- reserved@d200000 {
+ wcnss_region: wcnss@d200000 {
reg = <0x0d200000 0xa00000>;
no-map;
};
@@ -61,8 +62,11 @@
};
rmtfs@fd80000 {
+ compatible = "qcom,rmtfs-mem";
reg = <0x0fd80000 0x180000>;
no-map;
+
+ qcom,client-id = <1>;
};
};
@@ -356,6 +360,15 @@
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
+
+ smd-edge {
+ interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,ipc = <&apcs 8 8>;
+ qcom,smd-edge = <1>;
+
+ label = "lpass";
+ };
};
smem {
@@ -795,6 +808,119 @@
clock-names = "core";
};
+ remoteproc@fc880000 {
+ compatible = "qcom,msm8974-mss-pil";
+ reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
+ reg-names = "qdsp6", "rmb";
+
+ interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
+
+ clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
+ <&gcc GCC_MSS_CFG_AHB_CLK>,
+ <&gcc GCC_BOOT_ROM_AHB_CLK>,
+ <&xo_board>;
+ clock-names = "iface", "bus", "mem", "xo";
+
+ resets = <&gcc GCC_MSS_RESTART>;
+ reset-names = "mss_restart";
+
+ cx-supply = <&pm8841_s2>;
+ mss-supply = <&pm8841_s3>;
+ mx-supply = <&pm8841_s1>;
+ pll-supply = <&pm8941_l12>;
+
+ qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>;
+
+ qcom,smem-states = <&modem_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ mba {
+ memory-region = <&mba_region>;
+ };
+
+ mpss {
+ memory-region = <&mpss_region>;
+ };
+
+ smd-edge {
+ interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,ipc = <&apcs 8 12>;
+ qcom,smd-edge = <0>;
+
+ label = "modem";
+ };
+ };
+
+ pronto: remoteproc@fb21b000 {
+ compatible = "qcom,pronto-v2-pil", "qcom,pronto";
+ reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
+ reg-names = "ccu", "dxe", "pmu";
+
+ memory-region = <&wcnss_region>;
+
+ interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
+
+ vddpx-supply = <&pm8941_s3>;
+
+ qcom,smem-states = <&wcnss_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ iris {
+ compatible = "qcom,wcn3680";
+
+ clocks = <&rpmcc RPM_SMD_CXO_A2>;
+ clock-names = "xo";
+
+ vddxo-supply = <&pm8941_l6>;
+ vddrfa-supply = <&pm8941_l11>;
+ vddpa-supply = <&pm8941_l19>;
+ vdddig-supply = <&pm8941_s3>;
+ };
+
+ smd-edge {
+ interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,ipc = <&apcs 8 17>;
+ qcom,smd-edge = <6>;
+
+ wcnss {
+ compatible = "qcom,wcnss";
+ qcom,smd-channels = "WCNSS_CTRL";
+ status = "disabled";
+
+ qcom,mmio = <&pronto>;
+
+ bt {
+ compatible = "qcom,wcnss-bt";
+ };
+
+ wifi {
+ compatible = "qcom,wcnss-wlan";
+
+ interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "tx", "rx";
+
+ qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
+ qcom,smem-state-names = "tx-enable", "tx-rings-empty";
+ };
+ };
+ };
+ };
+
msmgpio: pinctrl@fd510000 {
compatible = "qcom,msm8974-pinctrl";
reg = <0xfd510000 0x4000>;
@@ -1179,6 +1305,79 @@
};
};
+ ocmem@fdd00000 {
+ compatible = "qcom,msm8974-ocmem";
+ reg = <0xfdd00000 0x2000>,
+ <0xfec00000 0x180000>;
+ reg-names = "ctrl",
+ "mem";
+ clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
+ <&mmcc OCMEMCX_OCMEMNOC_CLK>;
+ clock-names = "core",
+ "iface";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gmu_sram: gmu-sram@0 {
+ reg = <0x0 0x100000>;
+ };
+ };
+
+ bimc: interconnect@fc380000 {
+ reg = <0xfc380000 0x6a000>;
+ compatible = "qcom,msm8974-bimc";
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
+ <&rpmcc RPM_SMD_BIMC_A_CLK>;
+ };
+
+ snoc: interconnect@fc460000 {
+ reg = <0xfc460000 0x4000>;
+ compatible = "qcom,msm8974-snoc";
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
+ <&rpmcc RPM_SMD_SNOC_A_CLK>;
+ };
+
+ pnoc: interconnect@fc468000 {
+ reg = <0xfc468000 0x4000>;
+ compatible = "qcom,msm8974-pnoc";
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
+ <&rpmcc RPM_SMD_PNOC_A_CLK>;
+ };
+
+ ocmemnoc: interconnect@fc470000 {
+ reg = <0xfc470000 0x4000>;
+ compatible = "qcom,msm8974-ocmemnoc";
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
+ <&rpmcc RPM_SMD_OCMEMGX_A_CLK>;
+ };
+
+ mmssnoc: interconnect@fc478000 {
+ reg = <0xfc478000 0x4000>;
+ compatible = "qcom,msm8974-mmssnoc";
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&mmcc MMSS_S0_AXI_CLK>,
+ <&mmcc MMSS_S0_AXI_CLK>;
+ };
+
+ cnoc: interconnect@fc480000 {
+ reg = <0xfc480000 0x4000>;
+ compatible = "qcom,msm8974-cnoc";
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
+ <&rpmcc RPM_SMD_CNOC_A_CLK>;
+ };
+
mdss: mdss@fd900000 {
status = "disabled";
@@ -1225,6 +1424,9 @@
"core",
"vsync";
+ interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>;
+ interconnect-names = "mdp0-mem";
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -1325,20 +1527,6 @@
smd {
compatible = "qcom,smd";
- adsp {
- interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
-
- qcom,ipc = <&apcs 8 8>;
- qcom,smd-edge = <1>;
- };
-
- modem {
- interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
-
- qcom,ipc = <&apcs 8 12>;
- qcom,smd-edge = <0>;
- };
-
rpm {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 0>;
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index d03dcd919d6f..75b2796ebfca 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -313,9 +313,9 @@
mmcif: mmc@e804c800 {
compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
reg = <0xe804c800 0x80>;
- interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
power-domains = <&cpg_clocks>;
reg-io-width = <4>;
@@ -326,9 +326,9 @@
sdhi0: sd@e804e000 {
compatible = "renesas,sdhi-r7s72100";
reg = <0xe804e000 0x100>;
- interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
<&mstp12_clks R7S72100_CLK_SDHI01>;
@@ -342,9 +342,9 @@
sdhi1: sd@e804e800 {
compatible = "renesas,sdhi-r7s72100";
reg = <0xe804e800 0x100>;
- interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
<&mstp12_clks R7S72100_CLK_SDHI11>;
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index dd865f3c2eda..a5cd31229fbd 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -84,27 +84,27 @@
dma0: dma-controller@e6700020 {
compatible = "renesas,shdma-r8a73a4";
reg = <0 0xe6700020 0 0x89e0>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
index 758360a2edc3..d960c2767f61 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
@@ -60,8 +60,7 @@
enable-gpio = <&pfc 74 GPIO_ACTIVE_HIGH>;
gpios = <&pfc 17 GPIO_ACTIVE_HIGH>;
- states = <3300000 0
- 1800000 1>;
+ states = <3300000 0>, <1800000 1>;
enable-active-high;
};
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 12ffe73bf2bc..ebc1ff64f530 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -102,14 +102,14 @@
<0xe6900020 1>,
<0xe6900040 1>,
<0xe6900060 1>;
- interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
power-domains = <&pd_a4s>;
};
@@ -124,14 +124,14 @@
<0xe6900024 1>,
<0xe6900044 1>,
<0xe6900064 1>;
- interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
power-domains = <&pd_a4s>;
};
@@ -146,14 +146,14 @@
<0xe6900028 1>,
<0xe6900048 1>,
<0xe6900068 1>;
- interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
power-domains = <&pd_a4s>;
};
@@ -168,14 +168,14 @@
<0xe690002c 1>,
<0xe690004c 1>,
<0xe690006c 1>;
- interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
power-domains = <&pd_a4s>;
};
@@ -198,10 +198,10 @@
#size-cells = <0>;
compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
reg = <0xfff20000 0x425>;
- interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
power-domains = <&pd_a4r>;
status = "disabled";
@@ -212,10 +212,10 @@
#size-cells = <0>;
compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
reg = <0xe6c20000 0x425>;
- interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
power-domains = <&pd_a3sp>;
status = "disabled";
@@ -342,8 +342,8 @@
mmcif0: mmc@e6bd0000 {
compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif";
reg = <0xe6bd0000 0x100>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7740_CLK_MMC>;
power-domains = <&pd_a3sp>;
status = "disabled";
@@ -352,9 +352,9 @@
sdhi0: sd@e6850000 {
compatible = "renesas,sdhi-r8a7740";
reg = <0xe6850000 0x100>;
- interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
power-domains = <&pd_a3sp>;
cap-sd-highspeed;
@@ -365,9 +365,9 @@
sdhi1: sd@e6860000 {
compatible = "renesas,sdhi-r8a7740";
reg = <0xe6860000 0x100>;
- interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
power-domains = <&pd_a3sp>;
cap-sd-highspeed;
@@ -378,9 +378,9 @@
sdhi2: sd@e6870000 {
compatible = "renesas,sdhi-r8a7740";
reg = <0xe6870000 0x100>;
- interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
power-domains = <&pd_a3sp>;
cap-sd-highspeed;
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index de981d629bdd..1cd19a569bd0 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -399,6 +399,9 @@
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63a0000 0x12000>;
};
icram1: sram@e63c0000 {
@@ -417,6 +420,9 @@
icram2: sram@e6300000 {
compatible = "mmio-sram";
reg = <0 0xe6300000 0 0x40000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe6300000 0x40000>;
};
/* The memory map in the User's Manual maps the cores to
@@ -600,8 +606,8 @@
compatible = "renesas,r8a7743-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 330>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
@@ -614,8 +620,8 @@
compatible = "renesas,r8a7743-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 331>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
@@ -628,22 +634,22 @@
compatible = "renesas,dmac-r8a7743",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -661,22 +667,22 @@
compatible = "renesas,dmac-r8a7743",
"renesas,rcar-dmac";
reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1366,20 +1372,20 @@
compatible = "renesas,dmac-r8a7743",
"renesas,rcar-dmac";
reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1397,20 +1403,20 @@
compatible = "renesas,dmac-r8a7743",
"renesas,rcar-dmac";
reg = <0 0xec720000 0 0x10000>;
- interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1461,10 +1467,10 @@
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x800 0 0 0 0>;
@@ -1496,10 +1502,10 @@
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x10800 0 0 0 0>;
@@ -1611,13 +1617,13 @@
#size-cells = <2>;
bus-range = <0x00 0xff>;
device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
- 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
- 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
- 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
+ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
+ <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
+ <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
- 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>,
+ <0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index fa74a262107b..1c82dd0abd76 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -399,6 +399,9 @@
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63a0000 0x12000>;
};
icram1: sram@e63c0000 {
@@ -417,6 +420,9 @@
icram2: sram@e6300000 {
compatible = "mmio-sram";
reg = <0 0xe6300000 0 0x40000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe6300000 0x40000>;
};
/* The memory map in the User's Manual maps the cores to
@@ -600,8 +606,8 @@
compatible = "renesas,r8a7744-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 330>;
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
@@ -614,8 +620,8 @@
compatible = "renesas,r8a7744-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 331>;
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
@@ -628,22 +634,22 @@
compatible = "renesas,dmac-r8a7744",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -661,22 +667,22 @@
compatible = "renesas,dmac-r8a7744",
"renesas,rcar-dmac";
reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1366,20 +1372,20 @@
compatible = "renesas,dmac-r8a7744",
"renesas,rcar-dmac";
reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1397,20 +1403,20 @@
compatible = "renesas,dmac-r8a7744",
"renesas,rcar-dmac";
reg = <0 0xec720000 0 0x10000>;
- interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1461,10 +1467,10 @@
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x800 0 0 0 0>;
@@ -1496,10 +1502,10 @@
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x10800 0 0 0 0>;
@@ -1597,13 +1603,13 @@
#size-cells = <2>;
bus-range = <0x00 0xff>;
device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
- 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
- 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
- 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
+ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
+ <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
+ <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
- 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>,
+ <0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
index ce6603b0994b..58d369ad8279 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
@@ -76,8 +76,7 @@
gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
};
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index c53f7ff20695..3f88a7e34af2 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -363,6 +363,9 @@
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63a0000 0x12000>;
};
icram1: sram@e63c0000 {
@@ -381,6 +384,9 @@
icram2: sram@e6300000 {
compatible = "mmio-sram";
reg = <0 0xe6300000 0 0x40000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe6300000 0x40000>;
};
i2c0: i2c@e6508000 {
#address-cells = <1>;
@@ -543,8 +549,8 @@
compatible = "renesas,r8a7745-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 330>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
@@ -557,8 +563,8 @@
compatible = "renesas,r8a7745-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 331>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
@@ -571,22 +577,22 @@
compatible = "renesas,dmac-r8a7745",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -604,22 +610,22 @@
compatible = "renesas,dmac-r8a7745",
"renesas,rcar-dmac";
reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1293,20 +1299,20 @@
compatible = "renesas,dmac-r8a7745",
"renesas,rcar-dmac";
reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1337,10 +1343,10 @@
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x800 0 0 0 0>;
@@ -1372,10 +1378,10 @@
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x10800 0 0 0 0>;
diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
index 450efe923008..8ac61b50aec0 100644
--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -65,8 +65,7 @@
gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
};
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 51806c7f486a..6efcef1670e1 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -242,6 +242,9 @@
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63a0000 0x12000>;
};
icram1: sram@e63c0000 {
@@ -260,6 +263,9 @@
icram2: sram@e6300000 {
compatible = "mmio-sram";
reg = <0 0xe6300000 0 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe6300000 0x20000>;
};
i2c0: i2c@e6508000 {
@@ -407,8 +413,8 @@
compatible = "renesas,r8a77470-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 330>;
power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
@@ -421,8 +427,8 @@
compatible = "renesas,r8a77470-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 331>;
power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
@@ -435,8 +441,8 @@
compatible = "renesas,r8a77470-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65a8000 0 0x100>;
- interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 326>;
power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
@@ -449,8 +455,8 @@
compatible = "renesas,r8a77470-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65b8000 0 0x100>;
- interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 327>;
power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
@@ -463,22 +469,22 @@
compatible = "renesas,dmac-r8a77470",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -496,22 +502,22 @@
compatible = "renesas,dmac-r8a77470",
"renesas,rcar-dmac";
reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index 10d996d2941f..593c6df90303 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -79,10 +79,10 @@
<0xfe780024 4>,
<0xfe780044 4>,
<0xfe780064 4>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
sense-bitfield-width = <2>;
};
@@ -498,14 +498,17 @@
audio_clk_a: audio_clk_a {
compatible = "fixed-clock";
#clock-cells = <0>;
+ clock-frequency = <0>;
};
audio_clk_b: audio_clk_b {
compatible = "fixed-clock";
#clock-cells = <0>;
+ clock-frequency = <0>;
};
audio_clk_c: audio_clk_c {
compatible = "fixed-clock";
#clock-cells = <0>;
+ clock-frequency = <0>;
};
/* Fixed ratio clocks */
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index c755f0b8fd0d..d2240b89ee52 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -48,8 +48,7 @@
gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
ethernet@18000000 {
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index ebf5b7cfe215..beb9885e6ffc 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -68,6 +68,14 @@
<0xf0000100 0x100>;
};
+ timer@f0000200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0xf0000200 0x100>;
+ interrupts = <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
+ clocks = <&cpg_clocks R8A7779_CLK_ZS>;
+ };
+
timer@f0000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf0000600 0x20>;
@@ -164,10 +172,10 @@
<0xfe780044 4>,
<0xfe780064 4>,
<0xfe780000 4>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
sense-bitfield-width = <2>;
};
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 6ec2cf7eb354..097fd9317c6e 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -150,8 +150,7 @@
gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
vcc_sdhi2: regulator-vcc-sdhi2 {
@@ -174,8 +173,7 @@
gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
audio_clock: audio_clock {
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 5a2747758f67..334ba19769b9 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -487,6 +487,9 @@
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63a0000 0x12000>;
};
icram1: sram@e63c0000 {
@@ -669,8 +672,8 @@
compatible = "renesas,r8a7790-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 330>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
@@ -683,8 +686,8 @@
compatible = "renesas,r8a7790-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 331>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
@@ -697,22 +700,22 @@
compatible = "renesas,dmac-r8a7790",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -730,22 +733,22 @@
compatible = "renesas,dmac-r8a7790",
"renesas,rcar-dmac";
reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1300,20 +1303,20 @@
compatible = "renesas,dmac-r8a7790",
"renesas,rcar-dmac";
reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1331,20 +1334,20 @@
compatible = "renesas,dmac-r8a7790",
"renesas,rcar-dmac";
reg = <0 0xec720000 0 0x10000>;
- interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1388,10 +1391,10 @@
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x800 0 0 0 0>;
@@ -1423,10 +1426,10 @@
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
};
pci2: pci@ee0d0000 {
@@ -1446,10 +1449,10 @@
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x20800 0 0 0 0>;
@@ -1614,13 +1617,13 @@
#size-cells = <2>;
bus-range = <0x00 0xff>;
device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
- 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
- 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
- 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
+ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
+ <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
+ <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
- 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>,
+ <0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index af6bd8fcd5a4..2b096d5e06fb 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -193,8 +193,7 @@
gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
vcc_sdhi1: regulator-vcc-sdhi1 {
@@ -217,8 +216,7 @@
gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
vcc_sdhi2: regulator-vcc-sdhi2 {
@@ -241,8 +239,7 @@
gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
audio_clock: audio_clock {
diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts
index d6cf16aac14d..f9ece7ab2010 100644
--- a/arch/arm/boot/dts/r8a7791-porter.dts
+++ b/arch/arm/boot/dts/r8a7791-porter.dts
@@ -63,8 +63,7 @@
gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
vcc_sdhi2: regulator-vcc-sdhi2 {
@@ -85,8 +84,7 @@
gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
hdmi-out {
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 6f875502453c..59a55e87fcc6 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -420,6 +420,9 @@
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63a0000 0x12000>;
};
icram1: sram@e63c0000 {
@@ -618,8 +621,8 @@
compatible = "renesas,r8a7791-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 330>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
@@ -632,8 +635,8 @@
compatible = "renesas,r8a7791-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 331>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
@@ -646,22 +649,22 @@
compatible = "renesas,dmac-r8a7791",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -679,22 +682,22 @@
compatible = "renesas,dmac-r8a7791",
"renesas,rcar-dmac";
reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1338,20 +1341,20 @@
compatible = "renesas,dmac-r8a7791",
"renesas,rcar-dmac";
reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1369,20 +1372,20 @@
compatible = "renesas,dmac-r8a7791",
"renesas,rcar-dmac";
reg = <0 0xec720000 0 0x10000>;
- interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1426,10 +1429,10 @@
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x800 0 0 0 0>;
@@ -1461,10 +1464,10 @@
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x10800 0 0 0 0>;
@@ -1598,13 +1601,13 @@
#size-cells = <2>;
bus-range = <0x00 0xff>;
device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
- 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
- 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
- 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
+ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
+ <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
+ <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
- 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>,
+ <0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index c4ea2d676030..39af16caa2ae 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -345,6 +345,9 @@
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63a0000 0x12000>;
};
icram1: sram@e63c0000 {
@@ -466,22 +469,22 @@
compatible = "renesas,dmac-r8a7792",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -499,22 +502,22 @@
compatible = "renesas,dmac-r8a7792",
"renesas,rcar-dmac";
reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
index 48fbeb6340fd..22ca7cd1e7d2 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -179,8 +179,7 @@
gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
vcc_sdhi1: regulator-vcc-sdhi1 {
@@ -203,8 +202,7 @@
gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
vcc_sdhi2: regulator-vcc-sdhi2 {
@@ -227,8 +225,7 @@
gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
audio_clock: audio_clock {
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index bf05110fac4e..eef035c4d983 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -406,6 +406,9 @@
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63a0000 0x12000>;
};
icram1: sram@e63c0000 {
@@ -565,22 +568,22 @@
compatible = "renesas,dmac-r8a7793",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -598,22 +601,22 @@
compatible = "renesas,dmac-r8a7793",
"renesas,rcar-dmac";
reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1166,20 +1169,20 @@
compatible = "renesas,dmac-r8a7793",
"renesas,rcar-dmac";
reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1197,20 +1200,20 @@
compatible = "renesas,dmac-r8a7793",
"renesas,rcar-dmac";
reg = <0 0xec720000 0 0x10000>;
- interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 1d22fcdc5d22..f79fce74cd9c 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -60,8 +60,7 @@
gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
vcc_sdhi1: regulator-vcc-sdhi1 {
@@ -84,8 +83,7 @@
gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
lbsc {
diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
index b3177aea45d1..2c16ad854300 100644
--- a/arch/arm/boot/dts/r8a7794-silk.dts
+++ b/arch/arm/boot/dts/r8a7794-silk.dts
@@ -126,8 +126,7 @@
gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
vga-encoder {
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 8d797d34816e..05ef79c6ed7f 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -351,6 +351,9 @@
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63a0000 0x12000>;
};
icram1: sram@e63c0000 {
@@ -527,22 +530,22 @@
compatible = "renesas,dmac-r8a7794",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -560,22 +563,22 @@
compatible = "renesas,dmac-r8a7794",
"renesas,rcar-dmac";
reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1132,20 +1135,20 @@
compatible = "renesas,dmac-r8a7794",
"renesas,rcar-dmac";
reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3", "ch4",
"ch5", "ch6", "ch7", "ch8", "ch9",
@@ -1176,10 +1179,10 @@
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x800 0 0 0 0>;
@@ -1211,10 +1214,10 @@
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x10800 0 0 0 0>;
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index c70182c5aeb1..cf36e25195b4 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -224,7 +224,7 @@
status = "disabled";
};
- sdmmc: dwmmc@10214000 {
+ sdmmc: mmc@10214000 {
compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x10214000 0x4000>;
clock-frequency = <37500000>;
@@ -238,7 +238,7 @@
status = "disabled";
};
- sdio: dwmmc@10218000 {
+ sdio: mmc@10218000 {
compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x10218000 0x4000>;
max-frequency = <37500000>;
@@ -252,7 +252,7 @@
status = "disabled";
};
- emmc: dwmmc@1021c000 {
+ emmc: mmc@1021c000 {
compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x1021c000 0x4000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rk3188-bqedison2qc.dts
index c8b62bbd6a4a..ad1afd403052 100644
--- a/arch/arm/boot/dts/rk3188-bqedison2qc.dts
+++ b/arch/arm/boot/dts/rk3188-bqedison2qc.dts
@@ -466,9 +466,12 @@
pinctrl-names = "default";
pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_bus4>;
vmmcq-supply = <&vccio_wl>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "okay";
brcmf: wifi@1 {
+ reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio3>;
interrupts = <RK_PD2 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 340ed6ccb08f..4e90efdc9630 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -662,7 +662,7 @@
};
};
- sdmmc: dwmmc@30000000 {
+ sdmmc: mmc@30000000 {
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30000000 0x4000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
@@ -675,7 +675,7 @@
status = "disabled";
};
- sdio: dwmmc@30010000 {
+ sdio: mmc@30010000 {
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30010000 0x4000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
@@ -688,7 +688,7 @@
status = "disabled";
};
- emmc: dwmmc@30020000 {
+ emmc: mmc@30020000 {
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30020000 0x4000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
index 2afd686b2033..018802df4c0e 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -97,7 +97,7 @@
};
panel: panel {
- compatible = "lg,lp079qx1-sp0v", "simple-panel";
+ compatible = "lg,lp079qx1-sp0v";
backlight = <&backlight>;
enable-gpios = <&gpio7 RK_PA4 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&lcd_cs>;
diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi
index 0aeef23ca3db..312582c1bd37 100644
--- a/arch/arm/boot/dts/rk3288-tinker.dtsi
+++ b/arch/arm/boot/dts/rk3288-tinker.dtsi
@@ -113,6 +113,17 @@
cpu0-supply = <&vdd_cpu>;
};
+&cpu_opp_table {
+ opp-1704000000 {
+ opp-hz = /bits/ 64 <1704000000>;
+ opp-microvolt = <1350000>;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1400000>;
+ };
+};
+
&gmac {
assigned-clocks = <&cru SCLK_MAC>;
assigned-clock-parents = <&ext_gmac>;
@@ -175,7 +186,7 @@
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
+ regulator-max-microvolt = <1400000>;
regulator-name = "vdd_arm";
regulator-ramp-delay = <6000>;
regulator-state-mem {
diff --git a/arch/arm/boot/dts/rk3288-veyron-brain.dts b/arch/arm/boot/dts/rk3288-veyron-brain.dts
index 406146cbff29..aa33d09184ad 100644
--- a/arch/arm/boot/dts/rk3288-veyron-brain.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-brain.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "rk3288-veyron.dtsi"
+#include "rk3288-veyron-broadcom-bluetooth.dtsi"
/ {
model = "Google Brain";
@@ -40,6 +41,14 @@
};
&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+ >;
+
hdmi {
vcc50_hdmi_en: vcc50-hdmi-en {
rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi b/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi
new file mode 100644
index 000000000000..a10d25ac8f7b
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Veyron (and derivatives) fragment for the Broadcom 43450 bluetooth
+ * chip.
+ *
+ * Copyright 2019 Google, Inc
+ */
+
+&uart0 {
+ bluetooth {
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l>, <&bt_enable_l>,
+ <&bt_dev_wake>;
+
+ compatible = "brcm,bcm43540-bt";
+ host-wakeup-gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
+ device-wakeup-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+ max-speed = <3000000>;
+ brcm,bt-pcm-int-params = [01 02 00 01 01];
+ };
+};
diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
index ffb60f880b39..05112c25176d 100644
--- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
@@ -136,27 +136,6 @@
};
&pinctrl {
- pinctrl-0 = <
- /* Common for sleep and wake, but no owners */
- &ddr0_retention
- &ddrio_pwroff
- &global_pwroff
-
- /* Wake only */
- &suspend_l_wake
- &bt_dev_wake_awake
- >;
- pinctrl-1 = <
- /* Common for sleep and wake, but no owners */
- &ddr0_retention
- &ddrio_pwroff
- &global_pwroff
-
- /* Sleep only */
- &suspend_l_sleep
- &bt_dev_wake_sleep
- >;
-
buttons {
ap_lid_int_l: ap-lid-int-l {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
diff --git a/arch/arm/boot/dts/rk3288-veyron-edp.dtsi b/arch/arm/boot/dts/rk3288-veyron-edp.dtsi
index 300a7e32c978..32c0f10765dd 100644
--- a/arch/arm/boot/dts/rk3288-veyron-edp.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-edp.dtsi
@@ -54,7 +54,7 @@
};
panel: panel {
- compatible = "innolux,n116bge", "simple-panel";
+ compatible = "innolux,n116bge";
status = "okay";
power-supply = <&panel_regulator>;
backlight = <&backlight>;
diff --git a/arch/arm/boot/dts/rk3288-veyron-fievel.dts b/arch/arm/boot/dts/rk3288-veyron-fievel.dts
index 9a0f55085839..309b122b4d0d 100644
--- a/arch/arm/boot/dts/rk3288-veyron-fievel.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-fievel.dts
@@ -18,8 +18,6 @@
"google,veyron-fievel-rev0", "google,veyron-fievel",
"google,veyron", "rockchip,rk3288";
- /delete-node/ bt-activity;
-
vccsys: vccsys {
compatible = "regulator-fixed";
regulator-name = "vccsys";
@@ -215,7 +213,11 @@
"PHY_PMEB",
"PHY_INT",
- "REC_MODE_L",
+ /*
+ * RECOVERY_SW_L is Chrome OS ABI. Schematics call
+ * it REC_MODE_L.
+ */
+ "RECOVERY_SW_L",
"OTP_OUT",
"",
"USB_OTG_POWER_EN",
@@ -382,7 +384,11 @@
"PWR_LED1",
"TPM_INT_H",
"SPK_ON",
- "FW_WP_AP",
+ /*
+ * AP_FLASH_WP_L is Chrome OS ABI. Schematics call
+ * it FW_WP_AP.
+ */
+ "AP_FLASH_WP_L",
"",
"CPU_NMI",
diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
index a4966e505a2f..171ba6185b6d 100644
--- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
@@ -273,6 +273,28 @@
};
&pinctrl {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+
+ /* Wake only */
+ &suspend_l_wake
+ &bt_dev_wake_awake
+ >;
+ pinctrl-1 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+
+ /* Sleep only */
+ &suspend_l_sleep
+ &bt_dev_wake_sleep
+ >;
+
buck-5v {
drv_5v: drv-5v {
rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rk3288-veyron-jerry.dts
index a6ee44f0fe13..66f00d28801a 100644
--- a/arch/arm/boot/dts/rk3288-veyron-jerry.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-jerry.dts
@@ -418,6 +418,28 @@
};
&pinctrl {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+
+ /* Wake only */
+ &suspend_l_wake
+ &bt_dev_wake_awake
+ >;
+ pinctrl-1 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+
+ /* Sleep only */
+ &suspend_l_sleep
+ &bt_dev_wake_sleep
+ >;
+
buck-5v {
drv_5v: drv-5v {
rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/arch/arm/boot/dts/rk3288-veyron-mickey.dts b/arch/arm/boot/dts/rk3288-veyron-mickey.dts
index 06a6a9554c48..ffd1121d19be 100644
--- a/arch/arm/boot/dts/rk3288-veyron-mickey.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-mickey.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "rk3288-veyron.dtsi"
+#include "rk3288-veyron-broadcom-bluetooth.dtsi"
/ {
model = "Google Mickey";
@@ -411,6 +412,14 @@
};
&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+ >;
+
hdmi {
power_hdmi_on: power-hdmi-on {
rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
index c833716dbe48..383fad1a88a1 100644
--- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "rk3288-veyron-chromebook.dtsi"
+#include "rk3288-veyron-broadcom-bluetooth.dtsi"
/ {
model = "Google Minnie";
@@ -70,7 +71,7 @@
};
&panel {
- compatible = "auo,b101ean01", "simple-panel";
+ compatible = "auo,b101ean01";
/delete-node/ panel-timing;
@@ -344,6 +345,26 @@
};
&pinctrl {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+
+ /* Wake only */
+ &suspend_l_wake
+ >;
+ pinctrl-1 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+
+ /* Sleep only */
+ &suspend_l_sleep
+ >;
+
buck-5v {
drv_5v: drv-5v {
rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rk3288-veyron-pinky.dts
index f420499f300a..71e6629cc208 100644
--- a/arch/arm/boot/dts/rk3288-veyron-pinky.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-pinky.dts
@@ -64,6 +64,28 @@
};
&pinctrl {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+
+ /* Wake only */
+ &suspend_l_wake
+ &bt_dev_wake_awake
+ >;
+ pinctrl-1 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+
+ /* Sleep only */
+ &suspend_l_sleep
+ &bt_dev_wake_sleep
+ >;
+
/delete-node/ lcd;
backlight {
diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts
index 2f2989bc3f9c..e354c61a45e7 100644
--- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "rk3288-veyron-chromebook.dtsi"
+#include "rk3288-veyron-broadcom-bluetooth.dtsi"
#include "cros-ec-sbs.dtsi"
/ {
@@ -279,6 +280,26 @@
};
&pinctrl {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+
+ /* Wake only */
+ &suspend_l_wake
+ >;
+ pinctrl-1 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+
+ /* Sleep only */
+ &suspend_l_sleep
+ >;
+
buck-5v {
drv_5v: drv-5v {
rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/arch/arm/boot/dts/rk3288-veyron-tiger.dts b/arch/arm/boot/dts/rk3288-veyron-tiger.dts
index bebb230e592f..069f0c2c1fdf 100644
--- a/arch/arm/boot/dts/rk3288-veyron-tiger.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-tiger.dts
@@ -53,7 +53,7 @@
};
&panel {
- compatible = "auo,b101ean01", "simple-panel";
+ compatible = "auo,b101ean01";
/delete-node/ panel-timing;
diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
index 7525e3dd1fc1..54a6838d73f5 100644
--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
@@ -23,30 +23,6 @@
reg = <0x0 0x0 0x0 0x80000000>;
};
- bt_activity: bt-activity {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&bt_host_wake>;
-
- /*
- * HACK: until we have an LPM driver, we'll use an
- * ugly GPIO key to allow Bluetooth to wake from S3.
- * This is expected to only be used by BT modules that
- * use UART for comms. For BT modules that talk over
- * SDIO we should use a wakeup mechanism related to SDIO.
- *
- * Use KEY_RESERVED here since that will work as a wakeup but
- * doesn't get reported to higher levels (so doesn't confuse
- * Chrome).
- */
- bt-wake {
- label = "BT Wakeup";
- gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>;
- linux,code = <KEY_RESERVED>;
- wakeup-source;
- };
-
- };
power_button: power-button {
compatible = "gpio-keys";
@@ -82,22 +58,17 @@
clocks = <&rk808 RK808_CLKOUT1>;
clock-names = "ext_clock";
pinctrl-names = "default";
- pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>;
+ pinctrl-0 = <&wifi_enable_h>;
/*
- * Depending on the actual card populated GPIO4 D4 and D5
+ * Depending on the actual card populated GPIO4 D4
* correspond to one of these signals on the module:
*
* D4:
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
- *
- * D5:
- * - BT_I2S_WS_BT_RFDISABLE_L
- * - No connect
*/
- reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>,
- <&gpio4 RK_PD5 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
};
vcc_5v: vcc-5v {
@@ -481,26 +452,6 @@
};
&pinctrl {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <
- /* Common for sleep and wake, but no owners */
- &ddr0_retention
- &ddrio_pwroff
- &global_pwroff
-
- /* Wake only */
- &bt_dev_wake_awake
- >;
- pinctrl-1 = <
- /* Common for sleep and wake, but no owners */
- &ddr0_retention
- &ddrio_pwroff
- &global_pwroff
-
- /* Sleep only */
- &bt_dev_wake_sleep
- >;
-
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
bias-disable;
drive-strength = <8>;
@@ -622,6 +573,10 @@
bt_dev_wake_awake: bt-dev-wake-awake {
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>;
};
+
+ bt_dev_wake: bt-dev-wake {
+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
tpm {
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 415c75f5783c..9beb662166aa 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -247,7 +247,7 @@
ports = <&vopl_out>, <&vopb_out>;
};
- sdmmc: dwmmc@ff0c0000 {
+ sdmmc: mmc@ff0c0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
@@ -261,7 +261,7 @@
status = "disabled";
};
- sdio0: dwmmc@ff0d0000 {
+ sdio0: mmc@ff0d0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
@@ -275,7 +275,7 @@
status = "disabled";
};
- sdio1: dwmmc@ff0e0000 {
+ sdio1: mmc@ff0e0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
@@ -289,7 +289,7 @@
status = "disabled";
};
- emmc: dwmmc@ff0f0000 {
+ emmc: mmc@ff0f0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 97307a405e60..241f43e29c77 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -231,7 +231,7 @@
status = "disabled";
};
- mmc0: dwmmc@10214000 {
+ mmc0: mmc@10214000 {
compatible = "rockchip,rk2928-dw-mshc";
reg = <0x10214000 0x1000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
@@ -245,7 +245,7 @@
status = "disabled";
};
- mmc1: dwmmc@10218000 {
+ mmc1: mmc@10218000 {
compatible = "rockchip,rk2928-dw-mshc";
reg = <0x10218000 0x1000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
@@ -259,7 +259,7 @@
status = "disabled";
};
- emmc: dwmmc@1021c000 {
+ emmc: mmc@1021c000 {
compatible = "rockchip,rk2928-dw-mshc";
reg = <0x1021c000 0x1000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi
new file mode 100644
index 000000000000..df3712aedf8a
--- /dev/null
+++ b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2019 Radxa Limited
+ * Copyright (c) 2019 Amarula Solutions(India)
+ */
+
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+};
+
+&gmac {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+ i2c-scl-rising-time-ns = <140>;
+ i2c-scl-falling-time-ns = <30>;
+};
+
+&i2c2 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ hym8563: hym8563@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "hym8563";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ vqmmc-supply = <&vccio_sd>;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&pinctrl {
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins =
+ <4 RK_PD6 0 &pcfg_pull_up>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 5876690ee09e..1fd06e7cb983 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -456,7 +456,7 @@
#reset-cells = <1>;
};
- emmc: dwmmc@30110000 {
+ emmc: mmc@30110000 {
compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30110000 0x4000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
@@ -468,7 +468,7 @@
status = "disabled";
};
- sdio: dwmmc@30120000 {
+ sdio: mmc@30120000 {
compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30120000 0x4000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
@@ -480,7 +480,7 @@
status = "disabled";
};
- sdmmc: dwmmc@30130000 {
+ sdmmc: mmc@30130000 {
compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30130000 0x4000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts
index cb371bf72f64..811bfdef4e9b 100644
--- a/arch/arm/boot/dts/s3c2416-smdk2416.dts
+++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * SAMSUNG SMDK2416 board device tree source
+ * Samsung SMDK2416 board device tree source
*
* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
*/
diff --git a/arch/arm/boot/dts/s3c6410-smdk6410.dts b/arch/arm/boot/dts/s3c6410-smdk6410.dts
index 3bf6c450a26e..96267f5f02a8 100644
--- a/arch/arm/boot/dts/s3c6410-smdk6410.dts
+++ b/arch/arm/boot/dts/s3c6410-smdk6410.dts
@@ -4,7 +4,7 @@
*
* Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
*
- * Device tree source file for SAMSUNG SMDK6410 board which is based on
+ * Device tree source file for Samsung SMDK6410 board which is based on
* Samsung's S3C6410 SoC.
*/
@@ -16,7 +16,7 @@
#include "s3c6410.dtsi"
/ {
- model = "SAMSUNG SMDK6410 board based on S3C6410";
+ model = "Samsung SMDK6410 board based on S3C6410";
compatible = "samsung,mini6410", "samsung,s3c6410";
memory@50000000 {
diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi
new file mode 100644
index 000000000000..326b39328b58
--- /dev/null
+++ b/arch/arm/boot/dts/sam9x60.dtsi
@@ -0,0 +1,691 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC
+ *
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
+ */
+
+#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/mfd/atmel-flexcom.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "Microchip SAM9X60 SoC";
+ compatible = "microchip,sam9x60";
+ interrupt-parent = <&aic>;
+
+ aliases {
+ serial0 = &dbgu;
+ gpio0 = &pioA;
+ gpio1 = &pioB;
+ gpio2 = &pioC;
+ gpio3 = &pioD;
+ tcb0 = &tcb0;
+ tcb1 = &tcb1;
+ };
+
+ cpus {
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x20000000 0x10000000>;
+ };
+
+ clocks {
+ slow_xtal: slow_xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ main_xtal: main_xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+ };
+
+ sram: sram@300000 {
+ compatible = "mmio-sram";
+ reg = <0x00300000 0x100000>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ usb1: ohci@600000 {
+ compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+ reg = <0x00600000 0x100000>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
+ clock-names = "ohci_clk", "hclk", "uhpck";
+ status = "disabled";
+ };
+
+ usb2: ehci@700000 {
+ compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+ reg = <0x00700000 0x100000>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
+ clock-names = "usb_clk", "ehci_clk";
+ assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
+ assigned-clock-rates = <480000000>;
+ status = "disabled";
+ };
+
+ ebi: ebi@10000000 {
+ compatible = "microchip,sam9x60-ebi";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ atmel,smc = <&smc>;
+ microchip,sfr = <&sfr>;
+ reg = <0x10000000 0x60000000>;
+ ranges = <0x0 0x0 0x10000000 0x10000000
+ 0x1 0x0 0x20000000 0x10000000
+ 0x2 0x0 0x30000000 0x10000000
+ 0x3 0x0 0x40000000 0x10000000
+ 0x4 0x0 0x50000000 0x10000000
+ 0x5 0x0 0x60000000 0x10000000>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ status = "disabled";
+
+ nand_controller: nand-controller {
+ compatible = "microchip,sam9x60-nand-controller";
+ ecc-engine = <&pmecc>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+ };
+ };
+
+ sdmmc0: sdio-host@80000000 {
+ compatible = "microchip,sam9x60-sdhci";
+ reg = <0x80000000 0x300>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
+ clock-names = "hclock", "multclk";
+ assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
+ assigned-clock-rates = <100000000>;
+ status = "disabled";
+ };
+
+ sdmmc1: sdio-host@90000000 {
+ compatible = "microchip,sam9x60-sdhci";
+ reg = <0x90000000 0x300>;
+ interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
+ clock-names = "hclock", "multclk";
+ assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
+ assigned-clock-rates = <100000000>;
+ status = "disabled";
+ };
+
+ apb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ flx4: flexcom@f0000000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf0000000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf0000000 0x800>;
+ status = "disabled";
+ };
+
+ flx5: flexcom@f0004000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf0004000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf0004000 0x800>;
+ status = "disabled";
+ };
+
+ dma0: dma-controller@f0008000 {
+ compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma";
+ reg = <0xf0008000 0x1000>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
+ #dma-cells = <1>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
+ clock-names = "dma_clk";
+ };
+
+ ssc: ssc@f0010000 {
+ compatible = "atmel,at91sam9g45-ssc";
+ reg = <0xf0010000 0x4000>;
+ interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(38))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(39))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
+ clock-names = "pclk";
+ status = "disabled";
+ };
+
+ qspi: spi@f0014000 {
+ compatible = "microchip,sam9x60-qspi";
+ reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(26))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(27))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 19>;
+ clock-names = "pclk", "qspick";
+ atmel,pmc = <&pmc>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2s: i2s@f001c000 {
+ compatible = "microchip,sam9x60-i2smcc";
+ reg = <0xf001c000 0x100>;
+ interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(36))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(37))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>;
+ clock-names = "pclk", "gclk";
+ status = "disabled";
+ };
+
+ flx11: flexcom@f0020000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf0020000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf0020000 0x800>;
+ status = "disabled";
+ };
+
+ flx12: flexcom@f0024000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf0024000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf0024000 0x800>;
+ status = "disabled";
+ };
+
+ pit64b: timer@f0028000 {
+ compatible = "microchip,sam9x60-pit64b";
+ reg = <0xf0028000 0x100>;
+ interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
+ clock-names = "pclk", "gclk";
+ };
+
+ sha: sha@f002c000 {
+ compatible = "atmel,at91sam9g46-sha";
+ reg = <0xf002c000 0x100>;
+ interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(34))>;
+ dma-names = "tx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
+ clock-names = "sha_clk";
+ status = "okay";
+ };
+
+ trng: trng@f0030000 {
+ compatible = "microchip,sam9x60-trng";
+ reg = <0xf0030000 0x100>;
+ interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
+ status = "okay";
+ };
+
+ aes: aes@f0034000 {
+ compatible = "atmel,at91sam9g46-aes";
+ reg = <0xf0034000 0x100>;
+ interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(32))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(33))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
+ clock-names = "aes_clk";
+ status = "okay";
+ };
+
+ tdes: tdes@f0038000 {
+ compatible = "atmel,at91sam9g46-tdes";
+ reg = <0xf0038000 0x100>;
+ interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(31))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(30))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
+ clock-names = "tdes_clk";
+ status = "okay";
+ };
+
+ classd: classd@f003c000 {
+ compatible = "atmel,sama5d2-classd";
+ reg = <0xf003c000 0x100>;
+ interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(35))>;
+ dma-names = "tx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>;
+ clock-names = "pclk", "gclk";
+ status = "disabled";
+ };
+
+ can0: can@f8000000 {
+ compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
+ reg = <0xf8000000 0x300>;
+ interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
+ clock-names = "can_clk";
+ status = "disabled";
+ };
+
+ can1: can@f8004000 {
+ compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
+ reg = <0xf8004000 0x300>;
+ interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
+ clock-names = "can_clk";
+ status = "disabled";
+ };
+
+ tcb0: timer@f8008000 {
+ compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xf8008000 0x100>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
+ clock-names = "t0_clk", "slow_clk";
+ };
+
+ tcb1: timer@f800c000 {
+ compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xf800c000 0x100>;
+ interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>;
+ clock-names = "t0_clk", "slow_clk";
+ };
+
+ flx6: flexcom@f8010000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf8010000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf8010000 0x800>;
+ status = "disabled";
+ };
+
+ flx7: flexcom@f8014000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf8014000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf8014000 0x800>;
+ status = "disabled";
+ };
+
+ flx8: flexcom@f8018000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf8018000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf8018000 0x800>;
+ status = "disabled";
+ };
+
+ flx0: flexcom@f801c000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf801c000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf801c000 0x800>;
+ status = "disabled";
+ };
+
+ flx1: flexcom@f8020000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf8020000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf8020000 0x800>;
+ status = "disabled";
+ };
+
+ flx2: flexcom@f8024000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf8024000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf8024000 0x800>;
+ status = "disabled";
+ };
+
+ flx3: flexcom@f8028000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf8028000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf8028000 0x800>;
+ status = "disabled";
+ };
+
+ macb0: ethernet@f802c000 {
+ compatible = "cdns,sam9x60-macb", "cdns,macb";
+ reg = <0xf802c000 0x1000>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
+ clock-names = "hclk", "pclk";
+ status = "disabled";
+ };
+
+ macb1: ethernet@f8030000 {
+ compatible = "cdns,sam9x60-macb", "cdns,macb";
+ reg = <0xf8030000 0x1000>;
+ interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>;
+ clock-names = "hclk", "pclk";
+ status = "disabled";
+ };
+
+ pwm0: pwm@f8034000 {
+ compatible = "microchip,sam9x60-pwm";
+ reg = <0xf8034000 0x300>;
+ interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
+ #pwm-cells = <3>;
+ status="disabled";
+ };
+
+ hlcdc: hlcdc@f8038000 {
+ compatible = "microchip,sam9x60-hlcdc";
+ reg = <0xf8038000 0x4000>;
+ interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>;
+ clock-names = "periph_clk","sys_clk", "slow_clk";
+ assigned-clocks = <&pmc PMC_TYPE_GCK 25>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ status = "disabled";
+
+ hlcdc-display-controller {
+ compatible = "atmel,hlcdc-display-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ };
+
+ hlcdc_pwm: hlcdc-pwm {
+ compatible = "atmel,hlcdc-pwm";
+ #pwm-cells = <3>;
+ };
+ };
+
+ flx9: flexcom@f8040000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf8040000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf8040000 0x800>;
+ status = "disabled";
+ };
+
+ flx10: flexcom@f8044000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf8044000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf8044000 0x800>;
+ status = "disabled";
+ };
+
+ isi: isi@f8048000 {
+ compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi";
+ reg = <0xf8048000 0x100>;
+ interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
+ clock-names = "isi_clk";
+ status = "disabled";
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ adc: adc@f804c000 {
+ compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc";
+ reg = <0xf804c000 0x100>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
+ clock-names = "adc_clk";
+ dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
+ dma-names = "rx";
+ atmel,min-sample-rate-hz = <200000>;
+ atmel,max-sample-rate-hz = <20000000>;
+ atmel,startup-time-ms = <4>;
+ atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
+ sfr: sfr@f8050000 {
+ compatible = "microchip,sam9x60-sfr", "syscon";
+ reg = <0xf8050000 0x100>;
+ };
+
+ matrix: matrix@ffffde00 {
+ compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon";
+ reg = <0xffffde00 0x200>;
+ };
+
+ pmecc: ecc-engine@ffffe000 {
+ compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
+ reg = <0xffffe000 0x300>,
+ <0xffffe600 0x100>;
+ };
+
+ mpddrc: mpddrc@ffffe800 {
+ compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
+ reg = <0xffffe800 0x200>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clock-names = "ddrck", "mpddr";
+ };
+
+ smc: smc@ffffea00 {
+ compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
+ reg = <0xffffea00 0x100>;
+ };
+
+ aic: interrupt-controller@fffff100 {
+ compatible = "microchip,sam9x60-aic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xfffff100 0x100>;
+ atmel,external-irqs = <31>;
+ };
+
+ dbgu: serial@fffff200 {
+ compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+ reg = <0xfffff200 0x200>;
+ interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(28))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(29))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl@fffff400 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
+ ranges = <0xfffff400 0xfffff400 0x800>;
+
+ pioA: gpio@fffff400 {
+ compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfffff400 0x200>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
+ };
+
+ pioB: gpio@fffff600 {
+ compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfffff600 0x200>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #gpio-lines = <26>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
+ };
+
+ pioC: gpio@fffff800 {
+ compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfffff800 0x200>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
+ };
+
+ pioD: gpio@fffffa00 {
+ compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfffffa00 0x200>;
+ interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #gpio-lines = <22>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
+ };
+ };
+
+ pmc: pmc@fffffc00 {
+ compatible = "microchip,sam9x60-pmc", "syscon";
+ reg = <0xfffffc00 0x200>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ #clock-cells = <2>;
+ clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
+ clock-names = "td_slck", "md_slck", "main_xtal";
+ };
+
+ reset_controller: rstc@fffffe00 {
+ compatible = "microchip,sam9x60-rstc";
+ reg = <0xfffffe00 0x10>;
+ clocks = <&clk32k 0>;
+ };
+
+ shutdown_controller: shdwc@fffffe10 {
+ compatible = "microchip,sam9x60-shdwc";
+ reg = <0xfffffe10 0x10>;
+ clocks = <&clk32k 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ atmel,wakeup-rtc-timer;
+ atmel,wakeup-rtt-timer;
+ status = "disabled";
+ };
+
+ pit: timer@fffffe40 {
+ compatible = "atmel,at91sam9260-pit";
+ reg = <0xfffffe40 0x10>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ };
+
+ clk32k: sckc@fffffe50 {
+ compatible = "microchip,sam9x60-sckc";
+ reg = <0xfffffe50 0x4>;
+ clocks = <&slow_xtal>;
+ #clock-cells = <1>;
+ };
+
+ gpbr: syscon@fffffe60 {
+ compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon";
+ reg = <0xfffffe60 0x10>;
+ };
+
+ rtc: rtc@fffffea8 {
+ compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc";
+ reg = <0xfffffea8 0x100>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k 0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index 565204816e34..2012b7407c60 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -300,6 +300,8 @@
interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
clock-names = "hclock", "multclk", "baseclk";
+ assigned-clocks = <&pmc PMC_TYPE_GCK 31>;
+ assigned-clock-rates = <480000000>;
status = "disabled";
};
@@ -309,6 +311,8 @@
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
clock-names = "hclock", "multclk", "baseclk";
+ assigned-clocks = <&pmc PMC_TYPE_GCK 32>;
+ assigned-clock-rates = <480000000>;
status = "disabled";
};
@@ -615,6 +619,7 @@
interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>;
#pwm-cells = <3>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
+ status = "disabled";
};
sfr: sfr@f8030000 {
@@ -884,9 +889,12 @@
clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
};
- secumod@fc040000 {
+ pioBU: secumod@fc040000 {
compatible = "atmel,sama5d2-secumod", "syscon";
reg = <0xfc040000 0x100>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
};
tdes@fc044000 {
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index f770aace0efd..203d40be70a5 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -1188,49 +1188,49 @@
usart0_clk: usart0_clk {
#clock-cells = <0>;
reg = <12>;
- atmel,clk-output-range = <0 66000000>;
+ atmel,clk-output-range = <0 83000000>;
};
usart1_clk: usart1_clk {
#clock-cells = <0>;
reg = <13>;
- atmel,clk-output-range = <0 66000000>;
+ atmel,clk-output-range = <0 83000000>;
};
usart2_clk: usart2_clk {
#clock-cells = <0>;
reg = <14>;
- atmel,clk-output-range = <0 66000000>;
+ atmel,clk-output-range = <0 83000000>;
};
usart3_clk: usart3_clk {
#clock-cells = <0>;
reg = <15>;
- atmel,clk-output-range = <0 66000000>;
+ atmel,clk-output-range = <0 83000000>;
};
uart0_clk: uart0_clk {
#clock-cells = <0>;
reg = <16>;
- atmel,clk-output-range = <0 66000000>;
+ atmel,clk-output-range = <0 83000000>;
};
twi0_clk: twi0_clk {
reg = <18>;
#clock-cells = <0>;
- atmel,clk-output-range = <0 16625000>;
+ atmel,clk-output-range = <0 41500000>;
};
twi1_clk: twi1_clk {
#clock-cells = <0>;
reg = <19>;
- atmel,clk-output-range = <0 16625000>;
+ atmel,clk-output-range = <0 41500000>;
};
twi2_clk: twi2_clk {
#clock-cells = <0>;
reg = <20>;
- atmel,clk-output-range = <0 16625000>;
+ atmel,clk-output-range = <0 41500000>;
};
mci0_clk: mci0_clk {
@@ -1246,19 +1246,19 @@
spi0_clk: spi0_clk {
#clock-cells = <0>;
reg = <24>;
- atmel,clk-output-range = <0 133000000>;
+ atmel,clk-output-range = <0 166000000>;
};
spi1_clk: spi1_clk {
#clock-cells = <0>;
reg = <25>;
- atmel,clk-output-range = <0 133000000>;
+ atmel,clk-output-range = <0 166000000>;
};
tcb0_clk: tcb0_clk {
#clock-cells = <0>;
reg = <26>;
- atmel,clk-output-range = <0 133000000>;
+ atmel,clk-output-range = <0 166000000>;
};
pwm_clk: pwm_clk {
@@ -1269,7 +1269,7 @@
adc_clk: adc_clk {
#clock-cells = <0>;
reg = <29>;
- atmel,clk-output-range = <0 66000000>;
+ atmel,clk-output-range = <0 83000000>;
};
dma0_clk: dma0_clk {
@@ -1300,13 +1300,13 @@
ssc0_clk: ssc0_clk {
#clock-cells = <0>;
reg = <38>;
- atmel,clk-output-range = <0 66000000>;
+ atmel,clk-output-range = <0 83000000>;
};
ssc1_clk: ssc1_clk {
#clock-cells = <0>;
reg = <39>;
- atmel,clk-output-range = <0 66000000>;
+ atmel,clk-output-range = <0 83000000>;
};
sha_clk: sha_clk {
diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi
index cf06a018ed0f..2470dd3fff25 100644
--- a/arch/arm/boot/dts/sama5d3_can.dtsi
+++ b/arch/arm/boot/dts/sama5d3_can.dtsi
@@ -36,13 +36,13 @@
can0_clk: can0_clk {
#clock-cells = <0>;
reg = <40>;
- atmel,clk-output-range = <0 66000000>;
+ atmel,clk-output-range = <0 83000000>;
};
can1_clk: can1_clk {
#clock-cells = <0>;
reg = <41>;
- atmel,clk-output-range = <0 66000000>;
+ atmel,clk-output-range = <0 83000000>;
};
};
};
diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
index 1584035daf51..215802b8db30 100644
--- a/arch/arm/boot/dts/sama5d3_tcb1.dtsi
+++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
@@ -22,6 +22,7 @@
tcb1_clk: tcb1_clk {
#clock-cells = <0>;
reg = <27>;
+ atmel,clk-output-range = <0 166000000>;
};
};
};
diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi
index 4316bdbdc25d..cb62adbd28ed 100644
--- a/arch/arm/boot/dts/sama5d3_uart.dtsi
+++ b/arch/arm/boot/dts/sama5d3_uart.dtsi
@@ -41,13 +41,13 @@
uart0_clk: uart0_clk {
#clock-cells = <0>;
reg = <16>;
- atmel,clk-output-range = <0 66000000>;
+ atmel,clk-output-range = <0 83000000>;
};
uart1_clk: uart1_clk {
#clock-cells = <0>;
reg = <17>;
- atmel,clk-output-range = <0 66000000>;
+ atmel,clk-output-range = <0 83000000>;
};
};
};
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 33836990b102..c134154bcce8 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -39,11 +39,18 @@
};
};
+ timer@f0000200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0xf0000200 0x100>;
+ interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
+ clocks = <&periph_clk>;
+ };
+
timer@f0000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf0000600 0x20>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
- clocks = <&twd_clk>;
+ clocks = <&periph_clk>;
};
gic: interrupt-controller@f0001000 {
@@ -110,14 +117,14 @@
<0xe6900020 1>,
<0xe6900040 1>,
<0xe6900060 1>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
power-domains = <&pd_a4s>;
control-parent;
@@ -132,14 +139,14 @@
<0xe6900024 1>,
<0xe6900044 1>,
<0xe6900064 1>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
power-domains = <&pd_a4s>;
control-parent;
@@ -154,14 +161,14 @@
<0xe6900028 1>,
<0xe6900048 1>,
<0xe6900068 1>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
power-domains = <&pd_a4s>;
control-parent;
@@ -176,14 +183,14 @@
<0xe690002c 1>,
<0xe690004c 1>,
<0xe690006c 1>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
power-domains = <&pd_a4s>;
control-parent;
@@ -194,10 +201,10 @@
#size-cells = <0>;
compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
reg = <0xe6820000 0x425>;
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
power-domains = <&pd_a3sp>;
status = "disabled";
@@ -208,10 +215,10 @@
#size-cells = <0>;
compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
reg = <0xe6822000 0x425>;
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
power-domains = <&pd_a3sp>;
status = "disabled";
@@ -222,10 +229,10 @@
#size-cells = <0>;
compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
reg = <0xe6824000 0x425>;
- interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
power-domains = <&pd_a3sp>;
status = "disabled";
@@ -236,10 +243,10 @@
#size-cells = <0>;
compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
reg = <0xe6826000 0x425>;
- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
power-domains = <&pd_a3sp>;
status = "disabled";
@@ -250,10 +257,10 @@
#size-cells = <0>;
compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
reg = <0xe6828000 0x425>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
power-domains = <&pd_c5>;
status = "disabled";
@@ -262,8 +269,8 @@
mmcif: mmc@e6bd0000 {
compatible = "renesas,mmcif-sh73a0", "renesas,sh-mmcif";
reg = <0xe6bd0000 0x100>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
power-domains = <&pd_a3sp>;
reg-io-width = <4>;
@@ -317,9 +324,9 @@
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-sh73a0";
reg = <0xee100000 0x100>;
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
power-domains = <&pd_a3sp>;
cap-sd-highspeed;
@@ -330,8 +337,8 @@
sdhi1: sd@ee120000 {
compatible = "renesas,sdhi-sh73a0";
reg = <0xee120000 0x100>;
- interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
power-domains = <&pd_a3sp>;
disable-wp;
@@ -342,8 +349,8 @@
sdhi2: sd@ee140000 {
compatible = "renesas,sdhi-sh73a0";
reg = <0xee140000 0x100>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
power-domains = <&pd_a3sp>;
disable-wp;
@@ -612,19 +619,25 @@
extal2_clk: extal2 {
compatible = "fixed-clock";
#clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
};
extcki_clk: extcki {
compatible = "fixed-clock";
#clock-cells = <0>;
+ /* This value can be overridden by the board. */
+ clock-frequency = <0>;
};
fsiack_clk: fsiack {
compatible = "fixed-clock";
#clock-cells = <0>;
+ /* This value can be overridden by the board. */
clock-frequency = <0>;
};
fsibck_clk: fsibck {
compatible = "fixed-clock";
#clock-cells = <0>;
+ /* This value can be overridden by the board. */
clock-frequency = <0>;
};
@@ -812,7 +825,7 @@
clock-div = <13>;
clock-mult = <1>;
};
- twd_clk: twd {
+ periph_clk: periph {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks SH73A0_CLK_Z>;
#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/ste-ab8500.dtsi b/arch/arm/boot/dts/ste-ab8500.dtsi
index 55fff4d44277..14d4d8617d75 100644
--- a/arch/arm/boot/dts/ste-ab8500.dtsi
+++ b/arch/arm/boot/dts/ste-ab8500.dtsi
@@ -6,6 +6,20 @@
#include <dt-bindings/clock/ste-ab8500.h>
/ {
+ /* Essential housekeeping hardware monitors */
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&gpadc 0x02>, /* Battery temperature */
+ <&gpadc 0x03>, /* Main charger voltage */
+ <&gpadc 0x08>, /* Main battery voltage */
+ <&gpadc 0x09>, /* VBUS */
+ <&gpadc 0x0a>, /* Main charger current */
+ <&gpadc 0x0b>, /* USB charger current */
+ <&gpadc 0x0c>, /* Backup battery voltage */
+ <&gpadc 0x0d>, /* Die temperature */
+ <&gpadc 0x12>; /* Crystal temperature */
+ };
+
soc {
prcmu@80157000 {
ab8500 {
@@ -33,12 +47,84 @@
interrupt-names = "60S", "ALARM";
};
- ab8500-gpadc {
+ gpadc: ab8500-gpadc {
compatible = "stericsson,ab8500-gpadc";
interrupts = <32 IRQ_TYPE_LEVEL_HIGH
39 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "HW_CONV_END", "SW_CONV_END";
vddadc-supply = <&ab8500_ldo_tvout_reg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ /* GPADC channels */
+ bat_ctrl: channel@01 {
+ reg = <0x01>;
+ };
+ btemp_ball: channel@02 {
+ reg = <0x02>;
+ };
+ main_charger_v: channel@03 {
+ reg = <0x03>;
+ };
+ acc_detect1: channel@04 {
+ reg = <0x04>;
+ };
+ acc_detect2: channel@05 {
+ reg = <0x05>;
+ };
+ adc_aux1: channel@06 {
+ reg = <0x06>;
+ };
+ adc_aux2: channel@07 {
+ reg = <0x07>;
+ };
+ main_batt_v: channel@08 {
+ reg = <0x08>;
+ };
+ vbus_v: channel@09 {
+ reg = <0x09>;
+ };
+ main_charger_c: channel@0a {
+ reg = <0x0a>;
+ };
+ usb_charger_c: channel@0b {
+ reg = <0x0b>;
+ };
+ bk_bat_v: channel@0c {
+ reg = <0x0c>;
+ };
+ die_temp: channel@0d {
+ reg = <0x0d>;
+ };
+ usb_id: channel@0e {
+ reg = <0x0e>;
+ };
+ xtal_temp: channel@12 {
+ reg = <0x12>;
+ };
+ vbat_true_meas: channel@13 {
+ reg = <0x13>;
+ };
+ bat_ctrl_and_ibat: channel@1c {
+ reg = <0x1c>;
+ };
+ vbat_meas_and_ibat: channel@1d {
+ reg = <0x1d>;
+ };
+ vbat_true_meas_and_ibat: channel@1e {
+ reg = <0x1e>;
+ };
+ bat_temp_and_ibat: channel@1f {
+ reg = <0x1f>;
+ };
+ };
+
+ ab8500_temp {
+ compatible = "stericsson,abx500-temp";
+ io-channels = <&gpadc 0x06>,
+ <&gpadc 0x07>;
+ io-channel-name = "aux1", "aux2";
};
ab8500_battery: ab8500_battery {
@@ -49,17 +135,31 @@
ab8500_fg {
compatible = "stericsson,ab8500-fg";
battery = <&ab8500_battery>;
+ io-channels = <&gpadc 0x08>;
+ io-channel-name = "main_bat_v";
};
ab8500_btemp {
compatible = "stericsson,ab8500-btemp";
battery = <&ab8500_battery>;
+ io-channels = <&gpadc 0x02>,
+ <&gpadc 0x01>;
+ io-channel-name = "btemp_ball",
+ "bat_ctrl";
};
ab8500_charger {
compatible = "stericsson,ab8500-charger";
battery = <&ab8500_battery>;
vddadc-supply = <&ab8500_ldo_tvout_reg>;
+ io-channels = <&gpadc 0x03>,
+ <&gpadc 0x0a>,
+ <&gpadc 0x09>,
+ <&gpadc 0x0b>;
+ io-channel-name = "main_charger_v",
+ "main_charger_c",
+ "vbus_v",
+ "usb_charger_c";
};
ab8500_chargalg {
diff --git a/arch/arm/boot/dts/ste-ab8505.dtsi b/arch/arm/boot/dts/ste-ab8505.dtsi
new file mode 100644
index 000000000000..c72aa250bf6f
--- /dev/null
+++ b/arch/arm/boot/dts/ste-ab8505.dtsi
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2012 Linaro Ltd
+ */
+
+#include <dt-bindings/clock/ste-ab8500.h>
+
+/ {
+ /* Essential housekeeping hardware monitors */
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&gpadc 0x02>, /* Battery temperature */
+ <&gpadc 0x08>, /* Main battery voltage */
+ <&gpadc 0x09>, /* VBUS */
+ <&gpadc 0x0b>, /* Charger current */
+ <&gpadc 0x0c>; /* Backup battery voltage */
+ };
+
+ soc {
+ prcmu@80157000 {
+ ab8505 {
+ compatible = "stericsson,ab8505";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ ab8500_clock: clock-controller {
+ compatible = "stericsson,ab8500-clk";
+ #clock-cells = <1>;
+ };
+
+ ab8505_gpio: ab8505-gpio {
+ compatible = "stericsson,ab8505-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ ab8500-rtc {
+ compatible = "stericsson,ab8500-rtc";
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH
+ 18 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "60S", "ALARM";
+ };
+
+ gpadc: ab8500-gpadc {
+ compatible = "stericsson,ab8500-gpadc";
+ interrupts = <32 IRQ_TYPE_LEVEL_HIGH
+ 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "HW_CONV_END", "SW_CONV_END";
+ vddadc-supply = <&ab8500_ldo_adc_reg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ /* GPADC channels */
+ bat_ctrl: channel@01 {
+ reg = <0x01>;
+ };
+ btemp_ball: channel@02 {
+ reg = <0x02>;
+ };
+ acc_detect1: channel@04 {
+ reg = <0x04>;
+ };
+ acc_detect2: channel@05 {
+ reg = <0x05>;
+ };
+ adc_aux1: channel@06 {
+ reg = <0x06>;
+ };
+ adc_aux2: channel@07 {
+ reg = <0x07>;
+ };
+ main_batt_v: channel@08 {
+ reg = <0x08>;
+ };
+ vbus_v: channel@09 {
+ reg = <0x09>;
+ };
+ charger_c: channel@0b {
+ reg = <0x0b>;
+ };
+ bk_bat_v: channel@0c {
+ reg = <0x0c>;
+ };
+ usb_id: channel@0e {
+ reg = <0x0e>;
+ };
+ };
+
+ ab8500_battery: ab8500_battery {
+ status = "disabled";
+ thermistor-on-batctrl;
+ };
+
+ ab8500_fg {
+ status = "disabled";
+ compatible = "stericsson,ab8500-fg";
+ battery = <&ab8500_battery>;
+ io-channels = <&gpadc 0x08>;
+ io-channel-name = "main_bat_v";
+ };
+
+ ab8500_btemp {
+ status = "disabled";
+ compatible = "stericsson,ab8500-btemp";
+ battery = <&ab8500_battery>;
+ io-channels = <&gpadc 0x02>,
+ <&gpadc 0x01>;
+ io-channel-name = "btemp_ball",
+ "bat_ctrl";
+ };
+
+ ab8500_charger {
+ status = "disabled";
+ compatible = "stericsson,ab8500-charger";
+ battery = <&ab8500_battery>;
+ vddadc-supply = <&ab8500_ldo_adc_reg>;
+ io-channels = <&gpadc 0x09>,
+ <&gpadc 0x0b>;
+ io-channel-name = "vbus_v",
+ "usb_charger_c";
+ };
+
+ ab8500_chargalg {
+ status = "disabled";
+ compatible = "stericsson,ab8500-chargalg";
+ battery = <&ab8500_battery>;
+ };
+
+ ab8500_usb: ab8500_usb {
+ compatible = "stericsson,ab8500-usb";
+ interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
+ 96 IRQ_TYPE_LEVEL_HIGH
+ 14 IRQ_TYPE_LEVEL_HIGH
+ 15 IRQ_TYPE_LEVEL_HIGH
+ 79 IRQ_TYPE_LEVEL_HIGH
+ 74 IRQ_TYPE_LEVEL_HIGH
+ 75 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ID_WAKEUP_R",
+ "ID_WAKEUP_F",
+ "VBUS_DET_F",
+ "VBUS_DET_R",
+ "USB_LINK_STATUS",
+ "USB_ADP_PROBE_PLUG",
+ "USB_ADP_PROBE_UNPLUG";
+ vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
+ v-ape-supply = <&db8500_vape_reg>;
+ musb_1v8-supply = <&db8500_vsmps2_reg>;
+ clocks = <&prcmu_clk PRCMU_SYSCLK>;
+ clock-names = "sysclk";
+ };
+
+ ab8500-ponkey {
+ compatible = "stericsson,ab8500-poweron-key";
+ interrupts = <6 IRQ_TYPE_LEVEL_HIGH
+ 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
+ };
+
+ ab8500-sysctrl {
+ compatible = "stericsson,ab8500-sysctrl";
+ };
+
+ ab8500-pwm {
+ compatible = "stericsson,ab8500-pwm";
+ clocks = <&ab8500_clock AB8500_SYSCLK_INT>;
+ clock-names = "intclk";
+ };
+
+ ab8500-debugfs {
+ compatible = "stericsson,ab8500-debug";
+ };
+
+ codec: ab8500-codec {
+ compatible = "stericsson,ab8500-codec";
+
+ V-AUD-supply = <&ab8500_ldo_audio_reg>;
+ V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
+ V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
+
+ clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>;
+ clock-names = "audioclk";
+
+ stericsson,earpeice-cmv = <950>; /* Units in mV. */
+ };
+
+ ab8505-regulators {
+ compatible = "stericsson,ab8505-regulator";
+
+ ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ab8500_ldo_aux4_reg: ab8500_ldo_aux4 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ab8500_ldo_aux5_reg: ab8500_ldo_aux5 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <2790000>;
+ };
+
+ ab8500_ldo_aux6_reg: ab8500_ldo_aux6 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <2790000>;
+ };
+
+ // supply for v-intcore12; VINTCORE12 LDO
+ ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ // supply for gpadc; ADC LDO
+ ab8500_ldo_adc_reg: ab8500_ldo_adc {
+ };
+
+ // supply for ab8500-vaudio; VAUDIO LDO
+ ab8500_ldo_audio_reg: ab8500_ldo_audio {
+ };
+
+ // supply for v-anamic1 VAMIC1 LDO
+ ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
+ };
+
+ // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
+ ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
+ };
+
+ // supply for v-aux8; VAUX8 LDO
+ ab8500_ldo_aux8_reg: ab8500_ldo_aux8 {
+ };
+
+ // supply for U8500 CSI/DSI; VANA LDO
+ ab8500_ldo_ana_reg: ab8500_ldo_ana {
+ };
+ };
+ };
+ };
+
+ sound {
+ stericsson,audio-codec = <&codec>;
+ clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>;
+ clock-names = "sysclk", "ulpclk", "intclk";
+ };
+
+ mcde@a0350000 {
+ vana-supply = <&ab8500_ldo_ana_reg>;
+
+ dsi@a0351000 {
+ vana-supply = <&ab8500_ldo_ana_reg>;
+ };
+ dsi@a0352000 {
+ vana-supply = <&ab8500_ldo_ana_reg>;
+ };
+ dsi@a0353000 {
+ vana-supply = <&ab8500_ldo_ana_reg>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/ste-db8500.dtsi b/arch/arm/boot/dts/ste-db8500.dtsi
new file mode 100644
index 000000000000..d309fad32229
--- /dev/null
+++ b/arch/arm/boot/dts/ste-db8500.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "ste-dbx5x0.dtsi"
+
+/ {
+ cpus {
+ cpu@300 {
+ /* cpufreq controls */
+ operating-points = <998400 0
+ 800000 0
+ 400000 0
+ 200000 0>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/ste-db8520.dtsi b/arch/arm/boot/dts/ste-db8520.dtsi
new file mode 100644
index 000000000000..48bd8728ae27
--- /dev/null
+++ b/arch/arm/boot/dts/ste-db8520.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "ste-dbx5x0.dtsi"
+
+/ {
+ cpus {
+ cpu@300 {
+ /* cpufreq controls */
+ operating-points = <1152000 0
+ 800000 0
+ 400000 0
+ 200000 0>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi b/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi
new file mode 100644
index 000000000000..7bf7a2d34cbc
--- /dev/null
+++ b/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi
@@ -0,0 +1,632 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2013 Linaro Ltd.
+ */
+
+#include "ste-nomadik-pinctrl.dtsi"
+
+&pinctrl {
+ /* Settings for all UART default and sleep states */
+ uart0 {
+ u0_a_1_default: u0_a_1_default {
+ default_mux {
+ function = "u0";
+ groups = "u0_a_1";
+ };
+ default_cfg1 {
+ pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
+ ste,config = <&in_pu>;
+ };
+ default_cfg2 {
+ pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
+ ste,config = <&out_hi>;
+ };
+ };
+
+ u0_a_1_sleep: u0_a_1_sleep {
+ sleep_cfg1 {
+ pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
+ ste,config = <&slpm_in_wkup_pdis>;
+ };
+ sleep_cfg2 {
+ pins = "GPIO1_AJ3"; /* RTS */
+ ste,config = <&slpm_out_hi_wkup_pdis>;
+ };
+ sleep_cfg3 {
+ pins = "GPIO3_AH3"; /* TXD */
+ ste,config = <&slpm_out_wkup_pdis>;
+ };
+ };
+ };
+
+ uart1 {
+ u1rxtx_a_1_default: u1rxtx_a_1_default {
+ default_mux {
+ function = "u1";
+ groups = "u1rxtx_a_1";
+ };
+ default_cfg1 {
+ pins = "GPIO4_AH6"; /* RXD */
+ ste,config = <&in_pu>;
+ };
+ default_cfg2 {
+ pins = "GPIO5_AG6"; /* TXD */
+ ste,config = <&out_hi>;
+ };
+ };
+
+ u1rxtx_a_1_sleep: u1rxtx_a_1_sleep {
+ sleep_cfg1 {
+ pins = "GPIO4_AH6"; /* RXD */
+ ste,config = <&slpm_in_wkup_pdis>;
+ };
+ sleep_cfg2 {
+ pins = "GPIO5_AG6"; /* TXD */
+ ste,config = <&slpm_out_wkup_pdis>;
+ };
+ };
+
+ u1ctsrts_a_1_default: u1ctsrts_a_1_default {
+ default_mux {
+ function = "u1";
+ groups = "u1ctsrts_a_1";
+ };
+ default_cfg1 {
+ pins = "GPIO6_AF6"; /* CTS */
+ ste,config = <&in_pu>;
+ };
+ default_cfg2 {
+ pins = "GPIO7_AG5"; /* RTS */
+ ste,config = <&out_hi>;
+ };
+ };
+
+ u1ctsrts_a_1_sleep: u1ctsrts_a_1_sleep {
+ sleep_cfg1 {
+ pins = "GPIO6_AF6"; /* CTS */
+ ste,config = <&slpm_in_wkup_pdis>;
+ };
+ sleep_cfg2 {
+ pins = "GPIO7_AG5"; /* RTS */
+ ste,config = <&slpm_out_hi_wkup_pdis>;
+ };
+ };
+ };
+
+ uart2 {
+ u2rxtx_c_1_default: u2rxtx_c_1_default {
+ default_mux {
+ function = "u2";
+ groups = "u2rxtx_c_1";
+ };
+ default_cfg1 {
+ pins = "GPIO29_W2"; /* RXD */
+ ste,config = <&in_pu>;
+ };
+ default_cfg2 {
+ pins = "GPIO30_W3"; /* TXD */
+ ste,config = <&out_hi>;
+ };
+ };
+
+ u2rxtx_c_1_sleep: u2rxtx_c_1_sleep {
+ sleep_cfg1 {
+ pins = "GPIO29_W2"; /* RXD */
+ ste,config = <&in_wkup_pdis>;
+ };
+ sleep_cfg2 {
+ pins = "GPIO30_W3"; /* TXD */
+ ste,config = <&out_wkup_pdis>;
+ };
+ };
+ };
+
+ /* Settings for all I2C default and sleep states */
+ i2c0 {
+ i2c0_a_1_default: i2c0_a_1_default {
+ default_mux {
+ function = "i2c0";
+ groups = "i2c0_a_1";
+ };
+ default_cfg1 {
+ pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
+ ste,config = <&in_nopull>;
+ };
+ };
+
+ i2c0_a_1_sleep: i2c0_a_1_sleep {
+ sleep_cfg1 {
+ pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
+ ste,config = <&slpm_in_wkup_pdis>;
+ };
+ };
+ };
+
+ i2c1 {
+ i2c1_b_2_default: i2c1_b_2_default {
+ default_mux {
+ function = "i2c1";
+ groups = "i2c1_b_2";
+ };
+ default_cfg1 {
+ pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
+ ste,config = <&in_nopull>;
+ };
+ };
+
+ i2c1_b_2_sleep: i2c1_b_2_sleep {
+ sleep_cfg1 {
+ pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
+ ste,config = <&slpm_in_wkup_pdis>;
+ };
+ };
+ };
+
+ i2c2 {
+ i2c2_b_2_default: i2c2_b_2_default {
+ default_mux {
+ function = "i2c2";
+ groups = "i2c2_b_2";
+ };
+ default_cfg1 {
+ pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
+ ste,config = <&in_nopull>;
+ };
+ };
+
+ i2c2_b_2_sleep: i2c2_b_2_sleep {
+ sleep_cfg1 {
+ pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
+ ste,config = <&slpm_in_wkup_pdis>;
+ };
+ };
+ };
+
+ i2c3 {
+ i2c3_c_2_default: i2c3_c_2_default {
+ default_mux {
+ function = "i2c3";
+ groups = "i2c3_c_2";
+ };
+ default_cfg1 {
+ pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
+ ste,config = <&in_nopull>;
+ };
+ };
+
+ i2c3_c_2_sleep: i2c3_c_2_sleep {
+ sleep_cfg1 {
+ pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
+ ste,config = <&slpm_in_wkup_pdis>;
+ };
+ };
+ };
+
+ /*
+ * Activating I2C4 will conflict with UART1 about the same pins so do not
+ * enable I2C4 and UART1 at the same time.
+ */
+ i2c4 {
+ i2c4_b_1_default: i2c4_b_1_default {
+ default_mux {
+ function = "i2c4";
+ groups = "i2c4_b_1";
+ };
+ default_cfg1 {
+ pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
+ ste,config = <&in_nopull>;
+ };
+ };
+
+ i2c4_b_1_sleep: i2c4_b_1_sleep {
+ sleep_cfg1 {
+ pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
+ ste,config = <&slpm_in_wkup_pdis>;
+ };
+ };
+ };
+
+ /* Settings for all MMC/SD/SDIO default and sleep states */
+ sdi0 {
+ /* This is the external SD card slot, 4 bits wide */
+ mc0_a_1_default: mc0_a_1_default {
+ default_mux {
+ function = "mc0";
+ groups = "mc0_a_1";
+ };
+ default_cfg1 {
+ pins =
+ "GPIO18_AC2", /* CMDDIR */
+ "GPIO19_AC1", /* DAT0DIR */
+ "GPIO20_AB4"; /* DAT2DIR */
+ ste,config = <&out_hi>;
+ };
+ default_cfg2 {
+ pins = "GPIO22_AA3"; /* FBCLK */
+ ste,config = <&in_nopull>;
+ };
+ default_cfg3 {
+ pins = "GPIO23_AA4"; /* CLK */
+ ste,config = <&out_lo>;
+ };
+ default_cfg4 {
+ pins =
+ "GPIO24_AB2", /* CMD */
+ "GPIO25_Y4", /* DAT0 */
+ "GPIO26_Y2", /* DAT1 */
+ "GPIO27_AA2", /* DAT2 */
+ "GPIO28_AA1"; /* DAT3 */
+ ste,config = <&in_pu>;
+ };
+ };
+
+ mc0_a_1_sleep: mc0_a_1_sleep {
+ sleep_cfg1 {
+ pins =
+ "GPIO18_AC2", /* CMDDIR */
+ "GPIO19_AC1", /* DAT0DIR */
+ "GPIO20_AB4"; /* DAT2DIR */
+ ste,config = <&slpm_out_hi_wkup_pdis>;
+ };
+ sleep_cfg2 {
+ pins =
+ "GPIO22_AA3", /* FBCLK */
+ "GPIO24_AB2", /* CMD */
+ "GPIO25_Y4", /* DAT0 */
+ "GPIO26_Y2", /* DAT1 */
+ "GPIO27_AA2", /* DAT2 */
+ "GPIO28_AA1"; /* DAT3 */
+ ste,config = <&slpm_in_wkup_pdis>;
+ };
+ sleep_cfg3 {
+ pins = "GPIO23_AA4"; /* CLK */
+ ste,config = <&slpm_out_lo_wkup_pdis>;
+ };
+ };
+
+ mc0_a_2_default: mc0_a_2_default {
+ default_mux {
+ function = "mc0";
+ groups = "mc0_a_2";
+ };
+ default_cfg1 {
+ pins = "GPIO22_AA3"; /* FBCLK */
+ ste,config = <&in_nopull>;
+ };
+ default_cfg2 {
+ pins = "GPIO23_AA4"; /* CLK */
+ ste,config = <&out_lo>;
+ };
+ default_cfg3 {
+ pins =
+ "GPIO24_AB2", /* CMD */
+ "GPIO25_Y4", /* DAT0 */
+ "GPIO26_Y2", /* DAT1 */
+ "GPIO27_AA2", /* DAT2 */
+ "GPIO28_AA1"; /* DAT3 */
+ ste,config = <&in_pu>;
+ };
+ };
+
+ mc0_a_2_sleep: mc0_a_2_sleep {
+ sleep_cfg1 {
+ pins =
+ "GPIO22_AA3", /* FBCLK */
+ "GPIO24_AB2", /* CMD */
+ "GPIO25_Y4", /* DAT0 */
+ "GPIO26_Y2", /* DAT1 */
+ "GPIO27_AA2", /* DAT2 */
+ "GPIO28_AA1"; /* DAT3 */
+ ste,config = <&slpm_in_wkup_pdis>;
+ };
+ sleep_cfg2 {
+ pins = "GPIO23_AA4"; /* CLK */
+ ste,config = <&slpm_out_lo_wkup_pdis>;
+ };
+ };
+ };
+
+ sdi1 {
+ /* This is the WLAN SDIO 4 bits wide */
+ mc1_a_1_default: mc1_a_1_default {
+ default_mux {
+ function = "mc1";
+ groups = "mc1_a_1";
+ };
+ default_cfg1 {
+ pins = "GPIO208_AH16"; /* CLK */
+ ste,config = <&out_lo>;
+ };
+ default_cfg2 {
+ pins = "GPIO209_AG15"; /* FBCLK */
+ ste,config = <&in_nopull>;
+ };
+ default_cfg3 {
+ pins =
+ "GPIO210_AJ15", /* CMD */
+ "GPIO211_AG14", /* DAT0 */
+ "GPIO212_AF13", /* DAT1 */
+ "GPIO213_AG13", /* DAT2 */
+ "GPIO214_AH15"; /* DAT3 */
+ ste,config = <&in_pu>;
+ };
+ };
+
+ mc1_a_1_sleep: mc1_a_1_sleep {
+ sleep_cfg1 {
+ pins = "GPIO208_AH16"; /* CLK */
+ ste,config = <&slpm_out_lo_wkup_pdis>;
+ };
+ sleep_cfg2 {
+ pins =
+ "GPIO209_AG15", /* FBCLK */
+ "GPIO210_AJ15", /* CMD */
+ "GPIO211_AG14", /* DAT0 */
+ "GPIO212_AF13", /* DAT1 */
+ "GPIO213_AG13", /* DAT2 */
+ "GPIO214_AH15"; /* DAT3 */
+ ste,config = <&slpm_in_wkup_pdis>;
+ };
+ };
+
+ mc1_a_2_default: mc1_a_2_default {
+ default_mux {
+ function = "mc1";
+ groups = "mc1_a_2";
+ };
+ default_cfg1 {
+ pins = "GPIO208_AH16"; /* CLK */
+ ste,config = <&out_lo>;
+ };
+ default_cfg2 {
+ pins =
+ "GPIO210_AJ15", /* CMD */
+ "GPIO211_AG14", /* DAT0 */
+ "GPIO212_AF13", /* DAT1 */
+ "GPIO213_AG13", /* DAT2 */
+ "GPIO214_AH15"; /* DAT3 */
+ ste,config = <&in_pu>;
+ };
+ };
+
+ mc1_a_2_sleep: mc1_a_2_sleep {
+ sleep_cfg1 {
+ pins = "GPIO208_AH16"; /* CLK */
+ ste,config = <&slpm_out_lo_wkup_pdis>;
+ };
+ sleep_cfg2 {
+ pins =
+ "GPIO210_AJ15", /* CMD */
+ "GPIO211_AG14", /* DAT0 */
+ "GPIO212_AF13", /* DAT1 */
+ "GPIO213_AG13", /* DAT2 */
+ "GPIO214_AH15"; /* DAT3 */
+ ste,config = <&slpm_in_wkup_pdis>;
+ };
+ };
+ };
+
+ sdi2 {
+ /* This is the eMMC 8 bits wide, usually PoP eMMC */
+ mc2_a_1_default: mc2_a_1_default {
+ default_mux {
+ function = "mc2";
+ groups = "mc2_a_1";
+ };
+ default_cfg1 {
+ pins = "GPIO128_A5"; /* CLK */
+ ste,config = <&out_lo>;
+ };
+ default_cfg2 {
+ pins = "GPIO130_C8"; /* FBCLK */
+ ste,config = <&in_nopull>;
+ };
+ default_cfg3 {
+ pins =
+ "GPIO129_B4", /* CMD */
+ "GPIO131_A12", /* DAT0 */
+ "GPIO132_C10", /* DAT1 */
+ "GPIO133_B10", /* DAT2 */
+ "GPIO134_B9", /* DAT3 */
+ "GPIO135_A9", /* DAT4 */
+ "GPIO136_C7", /* DAT5 */
+ "GPIO137_A7", /* DAT6 */
+ "GPIO138_C5"; /* DAT7 */
+ ste,config = <&in_pu>;
+ };
+ };
+
+ mc2_a_1_sleep: mc2_a_1_sleep {
+ sleep_cfg1 {
+ pins = "GPIO128_A5"; /* CLK */
+ ste,config = <&out_lo_wkup_pdis>;
+ };
+ sleep_cfg2 {
+ pins =
+ "GPIO130_C8", /* FBCLK */
+ "GPIO129_B4"; /* CMD */
+ ste,config = <&in_wkup_pdis_en>;
+ };
+ sleep_cfg3 {
+ pins =
+ "GPIO131_A12", /* DAT0 */
+ "GPIO132_C10", /* DAT1 */
+ "GPIO133_B10", /* DAT2 */
+ "GPIO134_B9", /* DAT3 */
+ "GPIO135_A9", /* DAT4 */
+ "GPIO136_C7", /* DAT5 */
+ "GPIO137_A7", /* DAT6 */
+ "GPIO138_C5"; /* DAT7 */
+ ste,config = <&in_wkup_pdis>;
+ };
+ };
+ };
+
+ sdi4 {
+ /* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */
+ mc4_a_1_default: mc4_a_1_default {
+ default_mux {
+ function = "mc4";
+ groups = "mc4_a_1";
+ };
+ default_cfg1 {
+ pins = "GPIO203_AE23"; /* CLK */
+ ste,config = <&out_lo>;
+ };
+ default_cfg2 {
+ pins = "GPIO202_AF25"; /* FBCLK */
+ ste,config = <&in_nopull>;
+ };
+ default_cfg3 {
+ pins =
+ "GPIO201_AF24", /* CMD */
+ "GPIO200_AH26", /* DAT0 */
+ "GPIO199_AH23", /* DAT1 */
+ "GPIO198_AG25", /* DAT2 */
+ "GPIO197_AH24", /* DAT3 */
+ "GPIO207_AJ23", /* DAT4 */
+ "GPIO206_AG24", /* DAT5 */
+ "GPIO205_AG23", /* DAT6 */
+ "GPIO204_AF23"; /* DAT7 */
+ ste,config = <&in_pu>;
+ };
+ };
+
+ mc4_a_1_sleep: mc4_a_1_sleep {
+ sleep_cfg1 {
+ pins = "GPIO203_AE23"; /* CLK */
+ ste,config = <&out_lo_wkup_pdis>;
+ };
+ sleep_cfg2 {
+ pins =
+ "GPIO202_AF25", /* FBCLK */
+ "GPIO201_AF24", /* CMD */
+ "GPIO200_AH26", /* DAT0 */
+ "GPIO199_AH23", /* DAT1 */
+ "GPIO198_AG25", /* DAT2 */
+ "GPIO197_AH24", /* DAT3 */
+ "GPIO207_AJ23", /* DAT4 */
+ "GPIO206_AG24", /* DAT5 */
+ "GPIO205_AG23", /* DAT6 */
+ "GPIO204_AF23"; /* DAT7 */
+ ste,config = <&slpm_in_wkup_pdis>;
+ };
+ };
+ };
+
+ /*
+ * Multi-rate serial ports (MSPs) - MSP3 output is internal and
+ * cannot be muxed onto any pins.
+ */
+ msp0 {
+ msp0txrxtfstck_a_1_default: msp0txrxtfstck_a_1_default {
+ default_msp0_mux {
+ function = "msp0";
+ groups = "msp0txrx_a_1", "msp0tfstck_a_1";
+ };
+ default_msp0_cfg {
+ pins =
+ "GPIO12_AC4", /* TXD */
+ "GPIO15_AC3", /* RXD */
+ "GPIO13_AF3", /* TFS */
+ "GPIO14_AE3"; /* TCK */
+ ste,config = <&in_nopull>;
+ };
+ };
+ };
+
+ msp1 {
+ msp1txrx_a_1_default: msp1txrx_a_1_default {
+ default_mux {
+ function = "msp1";
+ groups = "msp1txrx_a_1", "msp1_a_1";
+ };
+ default_cfg1 {
+ pins = "GPIO33_AF2";
+ ste,config = <&out_lo>;
+ };
+ default_cfg2 {
+ pins =
+ "GPIO34_AE1",
+ "GPIO35_AE2",
+ "GPIO36_AG2";
+ ste,config = <&in_nopull>;
+ };
+ };
+ };
+
+ msp2 {
+ msp2_a_1_default: msp2_a_1_default {
+ /* MSP2 usually used for HDMI audio */
+ default_mux {
+ function = "msp2";
+ groups = "msp2_a_1";
+ };
+ default_cfg1 {
+ pins =
+ "GPIO193_AH27", /* TXD */
+ "GPIO194_AF27", /* TCK */
+ "GPIO195_AG28"; /* TFS */
+ ste,config = <&in_pd>;
+ };
+ default_cfg2 {
+ pins = "GPIO196_AG26"; /* RXD */
+ ste,config = <&out_lo>;
+ };
+ };
+ };
+
+ musb {
+ usb_a_1_default: usb_a_1_default {
+ default_mux {
+ function = "usb";
+ groups = "usb_a_1";
+ };
+ default_cfg1 {
+ pins =
+ "GPIO256_AF28", /* NXT */
+ "GPIO258_AD29", /* XCLK */
+ "GPIO259_AC29", /* DIR */
+ "GPIO260_AD28", /* DAT7 */
+ "GPIO261_AD26", /* DAT6 */
+ "GPIO262_AE26", /* DAT5 */
+ "GPIO263_AG29", /* DAT4 */
+ "GPIO264_AE27", /* DAT3 */
+ "GPIO265_AD27", /* DAT2 */
+ "GPIO266_AC28", /* DAT1 */
+ "GPIO267_AC27"; /* DAT0 */
+ ste,config = <&in_nopull>;
+ };
+ default_cfg2 {
+ pins = "GPIO257_AE29"; /* STP */
+ ste,config = <&out_hi>;
+ };
+ };
+
+ usb_a_1_sleep: usb_a_1_sleep {
+ sleep_cfg1 {
+ pins =
+ "GPIO256_AF28", /* NXT */
+ "GPIO258_AD29", /* XCLK */
+ "GPIO259_AC29"; /* DIR */
+ ste,config = <&slpm_wkup_pdis_en>;
+ };
+ sleep_cfg2 {
+ pins = "GPIO257_AE29"; /* STP */
+ ste,config = <&slpm_out_hi_wkup_pdis>;
+ };
+ sleep_cfg3 {
+ pins =
+ "GPIO260_AD28", /* DAT7 */
+ "GPIO261_AD26", /* DAT6 */
+ "GPIO262_AE26", /* DAT5 */
+ "GPIO263_AG29", /* DAT4 */
+ "GPIO264_AE27", /* DAT3 */
+ "GPIO265_AD27", /* DAT2 */
+ "GPIO266_AC28", /* DAT1 */
+ "GPIO267_AC27"; /* DAT0 */
+ ste,config = <&slpm_in_wkup_pdis_en>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index bda454d12150..6671f74c9f03 100644
--- a/arch/arm/boot/dts/ste-dbx5x0.dtsi
+++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi
@@ -14,6 +14,22 @@
#address-cells = <1>;
#size-cells = <1>;
+ /* This stablilizes the device enumeration */
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ spi2 = &spi2;
+ spi3 = &spi3;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ };
+
chosen {
};
@@ -36,11 +52,6 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x300>;
- /* cpufreq controls */
- operating-points = <998400 0
- 800000 0
- 400000 0
- 200000 0>;
clocks = <&prcmu_clk PRCMU_ARMSS>;
clock-names = "cpu";
clock-latency = <20000>;
@@ -93,7 +104,7 @@
soc {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "stericsson,db8500";
+ compatible = "stericsson,db8500", "simple-bus";
interrupt-parent = <&intc>;
ranges;
@@ -324,7 +335,7 @@
};
rtc@80154000 {
- compatible = "arm,rtc-pl031", "arm,primecell";
+ compatible = "arm,pl031", "arm,primecell";
reg = <0x80154000 0x1000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
@@ -638,7 +649,7 @@
};
};
- i2c@80004000 {
+ i2c0: i2c@80004000 {
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
reg = <0x80004000 0x1000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
@@ -651,9 +662,11 @@
clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
clock-names = "i2cclk", "apb_pclk";
power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
};
- i2c@80122000 {
+ i2c1: i2c@80122000 {
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
reg = <0x80122000 0x1000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
@@ -667,9 +680,11 @@
clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
clock-names = "i2cclk", "apb_pclk";
power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
};
- i2c@80128000 {
+ i2c2: i2c@80128000 {
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
reg = <0x80128000 0x1000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
@@ -683,9 +698,11 @@
clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
clock-names = "i2cclk", "apb_pclk";
power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
};
- i2c@80110000 {
+ i2c3: i2c@80110000 {
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
reg = <0x80110000 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
@@ -699,9 +716,11 @@
clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
clock-names = "i2cclk", "apb_pclk";
power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
};
- i2c@8012a000 {
+ i2c4: i2c@8012a000 {
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
reg = <0x8012a000 0x1000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
@@ -715,9 +734,11 @@
clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
clock-names = "i2cclk", "apb_pclk";
power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
};
- spi@80002000 {
+ ssp0: spi@80002000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x80002000 0x1000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
@@ -729,9 +750,11 @@
<&dma 8 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx";
power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
};
- spi@80003000 {
+ ssp1: spi@80003000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x80003000 0x1000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
@@ -743,9 +766,11 @@
<&dma 9 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx";
power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
};
- spi@8011a000 {
+ spi0: spi@8011a000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x8011a000 0x1000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
@@ -758,9 +783,11 @@
<&dma 0 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx";
power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
};
- spi@80112000 {
+ spi1: spi@80112000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x80112000 0x1000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
@@ -773,9 +800,11 @@
<&dma 35 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx";
power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
};
- spi@80111000 {
+ spi2: spi@80111000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x80111000 0x1000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
@@ -788,9 +817,11 @@
<&dma 33 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx";
power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
};
- spi@80129000 {
+ spi3: spi@80129000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x80129000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
@@ -803,9 +834,11 @@
<&dma 40 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx";
power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
};
- ux500_serial0: uart@80120000 {
+ serial0: uart@80120000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x80120000 0x1000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
@@ -820,7 +853,7 @@
status = "disabled";
};
- ux500_serial1: uart@80121000 {
+ serial1: uart@80121000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x80121000 0x1000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
@@ -835,7 +868,7 @@
status = "disabled";
};
- ux500_serial2: uart@80007000 {
+ serial2: uart@80007000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x80007000 0x1000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/ste-href-ab8505.dtsi b/arch/arm/boot/dts/ste-href-ab8505.dtsi
deleted file mode 100644
index 95cf38a008e9..000000000000
--- a/arch/arm/boot/dts/ste-href-ab8505.dtsi
+++ /dev/null
@@ -1,234 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2014 Linaro Ltd.
- */
-
-/ {
- soc {
- prcmu@80157000 {
- ab8505 {
- ab8505-gpio {
- /* Hog a few default settings */
- pinctrl-names = "default";
- pinctrl-0 = <&gpio2_default_mode>,
- <&gpio10_default_mode>,
- <&gpio11_default_mode>,
- <&gpio13_default_mode>,
- <&gpio34_default_mode>,
- <&gpio50_default_mode>,
- <&pwm_default_mode>,
- <&adi2_default_mode>,
- <&modsclsda_default_mode>,
- <&resethw_default_mode>,
- <&service_default_mode>;
-
- /*
- * Pins 2, 10, 11, 13, 34 and 50
- * are muxed in as GPIO, and configured as INPUT PULL DOWN
- */
- gpio2 {
- gpio2_default_mode: gpio2_default {
- default_mux {
- function = "gpio";
- groups = "gpio2_a_1";
- };
- default_cfg {
- pins = "GPIO2_R5";
- input-enable;
- bias-pull-down;
- };
- };
- };
- gpio10 {
- gpio10_default_mode: gpio10_default {
- default_mux {
- function = "gpio";
- groups = "gpio10_d_1";
- };
- default_cfg {
- pins = "GPIO10_B16";
- input-enable;
- bias-pull-down;
- };
- };
- };
- gpio11 {
- gpio11_default_mode: gpio11_default {
- default_mux {
- function = "gpio";
- groups = "gpio11_d_1";
- };
- default_cfg {
- pins = "GPIO11_B17";
- input-enable;
- bias-pull-down;
- };
- };
- };
- gpio13 {
- gpio13_default_mode: gpio13_default {
- default_mux {
- function = "gpio";
- groups = "gpio13_d_1";
- };
- default_cfg {
- pins = "GPIO13_D17";
- input-enable;
- bias-disable;
- };
- };
- };
- gpio34 {
- gpio34_default_mode: gpio34_default {
- default_mux {
- function = "gpio";
- groups = "gpio34_a_1";
- };
- default_cfg {
- pins = "GPIO34_H14";
- input-enable;
- bias-pull-down;
- };
- };
- };
- gpio50 {
- gpio50_default_mode: gpio50_default {
- default_mux {
- function = "gpio";
- groups = "gpio50_d_1";
- };
- default_cfg {
- pins = "GPIO50_L4";
- input-enable;
- bias-disable;
- };
- };
- };
- /* This sets up the PWM pin 14 */
- pwm {
- pwm_default_mode: pwm_default {
- default_mux {
- function = "pwmout";
- groups = "pwmout1_d_1";
- };
- default_cfg {
- pins = "GPIO14_C16";
- input-enable;
- bias-pull-down;
- };
- };
- };
- /* This sets up audio interface 2 */
- adi2 {
- adi2_default_mode: adi2_default {
- default_mux {
- function = "adi2";
- groups = "adi2_d_1";
- };
- default_cfg {
- pins = "GPIO17_P2",
- "GPIO18_N3",
- "GPIO19_T1",
- "GPIO20_P3";
- input-enable;
- bias-pull-down;
- };
- };
- };
- /* Modem I2C setup (SCL and SDA pins) */
- modsclsda {
- modsclsda_default_mode: modsclsda_default {
- default_mux {
- function = "modsclsda";
- groups = "modsclsda_d_1";
- };
- default_cfg {
- pins = "GPIO40_J15",
- "GPIO41_J14";
- input-enable;
- bias-pull-down;
- };
- };
- };
- resethw {
- resethw_default_mode: resethw_default {
- default_mux {
- function = "resethw";
- groups = "resethw_d_1";
- };
- default_cfg {
- pins = "GPIO52_D16";
- input-enable;
- bias-pull-down;
- };
- };
- };
- service {
- service_default_mode: service_default {
- default_mux {
- function = "service";
- groups = "service_d_1";
- };
- default_cfg {
- pins = "GPIO53_D15";
- input-enable;
- bias-pull-down;
- };
- };
- };
- /*
- * Clock output pins associated with regulators.
- */
- sysclkreq2 {
- sysclkreq2_default_mode: sysclkreq2_default {
- default_mux {
- function = "sysclkreq";
- groups = "sysclkreq2_d_1";
- };
- default_cfg {
- pins = "GPIO1_N4";
- input-enable;
- bias-disable;
- };
- };
- sysclkreq2_sleep_mode: sysclkreq2_sleep {
- default_mux {
- function = "gpio";
- groups = "gpio1_a_1";
- };
- default_cfg {
- pins = "GPIO1_N4";
- input-enable;
- bias-pull-down;
- };
- };
- };
- sysclkreq4 {
- sysclkreq4_default_mode: sysclkreq4_default {
- default_mux {
- function = "sysclkreq";
- groups = "sysclkreq4_d_1";
- };
- default_cfg {
- pins = "GPIO3_P5";
- input-enable;
- bias-disable;
- };
- };
- sysclkreq4_sleep_mode: sysclkreq4_sleep {
- default_mux {
- function = "gpio";
- groups = "gpio3_a_1";
- };
- default_cfg {
- pins = "GPIO3_P5";
- input-enable;
- bias-pull-down;
- };
- };
- };
- };
- };
- };
- };
-};
diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
index 2c382d274ff6..434fa6baf71f 100644
--- a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
+++ b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
@@ -3,212 +3,11 @@
* Copyright 2013 Linaro Ltd.
*/
-#include "ste-nomadik-pinctrl.dtsi"
+#include "ste-dbx5x0-pinctrl.dtsi"
/ {
soc {
pinctrl {
- /* Settings for all UART default and sleep states */
- uart0 {
- uart0_default_mode: uart0_default {
- default_mux {
- function = "u0";
- groups = "u0_a_1";
- };
- default_cfg1 {
- pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
- ste,config = <&in_pu>;
- };
-
- default_cfg2 {
- pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
- ste,config = <&out_hi>;
- };
- };
-
- uart0_sleep_mode: uart0_sleep {
- sleep_cfg1 {
- pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
- ste,config = <&slpm_in_wkup_pdis>;
- };
-
- sleep_cfg2 {
- pins = "GPIO1_AJ3"; /* RTS */
- ste,config = <&slpm_out_hi_wkup_pdis>;
- };
-
- sleep_cfg3 {
- pins = "GPIO3_AH3"; /* TXD */
- ste,config = <&slpm_out_wkup_pdis>;
- };
- };
- };
-
- uart1 {
- uart1_default_mode: uart1_default {
- default_mux {
- function = "u1";
- groups = "u1rxtx_a_1";
- };
- default_cfg1 {
- pins = "GPIO4_AH6"; /* RXD */
- ste,config = <&in_pu>;
- };
-
- default_cfg2 {
- pins = "GPIO5_AG6"; /* TXD */
- ste,config = <&out_hi>;
- };
- };
-
- uart1_sleep_mode: uart1_sleep {
- sleep_cfg1 {
- pins = "GPIO4_AH6"; /* RXD */
- ste,config = <&slpm_in_wkup_pdis>;
- };
-
- sleep_cfg2 {
- pins = "GPIO5_AG6"; /* TXD */
- ste,config = <&slpm_out_wkup_pdis>;
- };
- };
- };
-
- uart2 {
- uart2_default_mode: uart2_default {
- default_mux {
- function = "u2";
- groups = "u2rxtx_c_1";
- };
- default_cfg1 {
- pins = "GPIO29_W2"; /* RXD */
- ste,config = <&in_pu>;
- };
-
- default_cfg2 {
- pins = "GPIO30_W3"; /* TXD */
- ste,config = <&out_hi>;
- };
- };
-
- uart2_sleep_mode: uart2_sleep {
- sleep_cfg1 {
- pins = "GPIO29_W2"; /* RXD */
- ste,config = <&in_wkup_pdis>;
- };
-
- sleep_cfg2 {
- pins = "GPIO30_W3"; /* TXD */
- ste,config = <&out_wkup_pdis>;
- };
- };
- };
-
- /* Settings for all I2C default and sleep states */
- i2c0 {
- i2c0_default_mode: i2c_default {
- default_mux {
- function = "i2c0";
- groups = "i2c0_a_1";
- };
- default_cfg1 {
- pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
- ste,config = <&in_pu>;
- };
- };
-
- i2c0_sleep_mode: i2c_sleep {
- sleep_cfg1 {
- pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
- ste,config = <&slpm_in_wkup_pdis>;
- };
- };
- };
-
- i2c1 {
- i2c1_default_mode: i2c_default {
- default_mux {
- function = "i2c1";
- groups = "i2c1_b_2";
- };
- default_cfg1 {
- pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
- ste,config = <&in_pu>;
- };
- };
-
- i2c1_sleep_mode: i2c_sleep {
- sleep_cfg1 {
- pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
- ste,config = <&slpm_in_wkup_pdis>;
- };
- };
- };
-
- i2c2 {
- i2c2_default_mode: i2c_default {
- default_mux {
- function = "i2c2";
- groups = "i2c2_b_2";
- };
- default_cfg1 {
- pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
- ste,config = <&in_pu>;
- };
- };
-
- i2c2_sleep_mode: i2c_sleep {
- sleep_cfg1 {
- pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
- ste,config = <&slpm_in_wkup_pdis>;
- };
- };
- };
-
- i2c3 {
- i2c3_default_mode: i2c_default {
- default_mux {
- function = "i2c3";
- groups = "i2c3_c_2";
- };
- default_cfg1 {
- pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
- ste,config = <&in_pu>;
- };
- };
-
- i2c3_sleep_mode: i2c_sleep {
- sleep_cfg1 {
- pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
- ste,config = <&slpm_in_wkup_pdis>;
- };
- };
- };
-
- /*
- * Activating I2C4 will conflict with UART1 about the same pins so do not
- * enable I2C4 and UART1 at the same time.
- */
- i2c4 {
- i2c4_default_mode: i2c_default {
- default_mux {
- function = "i2c4";
- groups = "i2c4_b_1";
- };
- default_cfg1 {
- pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
- ste,config = <&in_pu>;
- };
- };
-
- i2c4_sleep_mode: i2c_sleep {
- sleep_cfg1 {
- pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
- ste,config = <&slpm_in_wkup_pdis>;
- };
- };
- };
-
/* Settings for all SPI default and sleep states */
spi2 {
spi2_default_mode: spi_default {
@@ -270,335 +69,6 @@
};
};
- /* Settings for all MMC/SD/SDIO default and sleep states */
- sdi0 {
- /* This is the external SD card slot, 4 bits wide */
- sdi0_default_mode: sdi0_default {
- default_mux {
- function = "mc0";
- groups = "mc0_a_1";
- };
- default_cfg1 {
- pins =
- "GPIO18_AC2", /* CMDDIR */
- "GPIO19_AC1", /* DAT0DIR */
- "GPIO20_AB4"; /* DAT2DIR */
- ste,config = <&out_hi>;
- };
- default_cfg2 {
- pins = "GPIO22_AA3"; /* FBCLK */
- ste,config = <&in_nopull>;
- };
- default_cfg3 {
- pins = "GPIO23_AA4"; /* CLK */
- ste,config = <&out_lo>;
- };
- default_cfg4 {
- pins =
- "GPIO24_AB2", /* CMD */
- "GPIO25_Y4", /* DAT0 */
- "GPIO26_Y2", /* DAT1 */
- "GPIO27_AA2", /* DAT2 */
- "GPIO28_AA1"; /* DAT3 */
- ste,config = <&in_pu>;
- };
- };
-
- sdi0_sleep_mode: sdi0_sleep {
- sleep_cfg1 {
- pins =
- "GPIO18_AC2", /* CMDDIR */
- "GPIO19_AC1", /* DAT0DIR */
- "GPIO20_AB4"; /* DAT2DIR */
- ste,config = <&slpm_out_hi_wkup_pdis>;
- };
- sleep_cfg2 {
- pins =
- "GPIO22_AA3", /* FBCLK */
- "GPIO24_AB2", /* CMD */
- "GPIO25_Y4", /* DAT0 */
- "GPIO26_Y2", /* DAT1 */
- "GPIO27_AA2", /* DAT2 */
- "GPIO28_AA1"; /* DAT3 */
- ste,config = <&slpm_in_wkup_pdis>;
- };
- sleep_cfg3 {
- pins = "GPIO23_AA4"; /* CLK */
- ste,config = <&slpm_out_lo_wkup_pdis>;
- };
- };
- };
-
- sdi1 {
- /* This is the WLAN SDIO 4 bits wide */
- sdi1_default_mode: sdi1_default {
- default_mux {
- function = "mc1";
- groups = "mc1_a_1";
- };
- default_cfg1 {
- pins = "GPIO208_AH16"; /* CLK */
- ste,config = <&out_lo>;
- };
- default_cfg2 {
- pins = "GPIO209_AG15"; /* FBCLK */
- ste,config = <&in_nopull>;
- };
- default_cfg3 {
- pins =
- "GPIO210_AJ15", /* CMD */
- "GPIO211_AG14", /* DAT0 */
- "GPIO212_AF13", /* DAT1 */
- "GPIO213_AG13", /* DAT2 */
- "GPIO214_AH15"; /* DAT3 */
- ste,config = <&in_pu>;
- };
- };
-
- sdi1_sleep_mode: sdi1_sleep {
- sleep_cfg1 {
- pins = "GPIO208_AH16"; /* CLK */
- ste,config = <&slpm_out_lo_wkup_pdis>;
- };
- sleep_cfg2 {
- pins =
- "GPIO209_AG15", /* FBCLK */
- "GPIO210_AJ15", /* CMD */
- "GPIO211_AG14", /* DAT0 */
- "GPIO212_AF13", /* DAT1 */
- "GPIO213_AG13", /* DAT2 */
- "GPIO214_AH15"; /* DAT3 */
- ste,config = <&slpm_in_wkup_pdis>;
- };
- };
- };
-
- sdi2 {
- /* This is the eMMC 8 bits wide, usually PoP eMMC */
- sdi2_default_mode: sdi2_default {
- default_mux {
- function = "mc2";
- groups = "mc2_a_1";
- };
- default_cfg1 {
- pins = "GPIO128_A5"; /* CLK */
- ste,config = <&out_lo>;
- };
- default_cfg2 {
- pins = "GPIO130_C8"; /* FBCLK */
- ste,config = <&in_nopull>;
- };
- default_cfg3 {
- pins =
- "GPIO129_B4", /* CMD */
- "GPIO131_A12", /* DAT0 */
- "GPIO132_C10", /* DAT1 */
- "GPIO133_B10", /* DAT2 */
- "GPIO134_B9", /* DAT3 */
- "GPIO135_A9", /* DAT4 */
- "GPIO136_C7", /* DAT5 */
- "GPIO137_A7", /* DAT6 */
- "GPIO138_C5"; /* DAT7 */
- ste,config = <&in_pu>;
- };
- };
-
- sdi2_sleep_mode: sdi2_sleep {
- sleep_cfg1 {
- pins = "GPIO128_A5"; /* CLK */
- ste,config = <&out_lo_wkup_pdis>;
- };
- sleep_cfg2 {
- pins =
- "GPIO130_C8", /* FBCLK */
- "GPIO129_B4"; /* CMD */
- ste,config = <&in_wkup_pdis_en>;
- };
- sleep_cfg3 {
- pins =
- "GPIO131_A12", /* DAT0 */
- "GPIO132_C10", /* DAT1 */
- "GPIO133_B10", /* DAT2 */
- "GPIO134_B9", /* DAT3 */
- "GPIO135_A9", /* DAT4 */
- "GPIO136_C7", /* DAT5 */
- "GPIO137_A7", /* DAT6 */
- "GPIO138_C5"; /* DAT7 */
- ste,config = <&in_wkup_pdis>;
- };
- };
- };
-
- sdi4 {
- /* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */
- sdi4_default_mode: sdi4_default {
- default_mux {
- function = "mc4";
- groups = "mc4_a_1";
- };
- default_cfg1 {
- pins = "GPIO203_AE23"; /* CLK */
- ste,config = <&out_lo>;
- };
- default_cfg2 {
- pins = "GPIO202_AF25"; /* FBCLK */
- ste,config = <&in_nopull>;
- };
- default_cfg3 {
- pins =
- "GPIO201_AF24", /* CMD */
- "GPIO200_AH26", /* DAT0 */
- "GPIO199_AH23", /* DAT1 */
- "GPIO198_AG25", /* DAT2 */
- "GPIO197_AH24", /* DAT3 */
- "GPIO207_AJ23", /* DAT4 */
- "GPIO206_AG24", /* DAT5 */
- "GPIO205_AG23", /* DAT6 */
- "GPIO204_AF23"; /* DAT7 */
- ste,config = <&in_pu>;
- };
- };
-
- sdi4_sleep_mode: sdi4_sleep {
- sleep_cfg1 {
- pins = "GPIO203_AE23"; /* CLK */
- ste,config = <&out_lo_wkup_pdis>;
- };
- sleep_cfg2 {
- pins =
- "GPIO202_AF25", /* FBCLK */
- "GPIO201_AF24", /* CMD */
- "GPIO200_AH26", /* DAT0 */
- "GPIO199_AH23", /* DAT1 */
- "GPIO198_AG25", /* DAT2 */
- "GPIO197_AH24", /* DAT3 */
- "GPIO207_AJ23", /* DAT4 */
- "GPIO206_AG24", /* DAT5 */
- "GPIO205_AG23", /* DAT6 */
- "GPIO204_AF23"; /* DAT7 */
- ste,config = <&slpm_in_wkup_pdis>;
- };
- };
- };
-
- /*
- * Multi-rate serial ports (MSPs) - MSP3 output is internal and
- * cannot be muxed onto any pins.
- */
- msp0 {
- msp0_default_mode: msp0_default {
- default_msp0_mux {
- function = "msp0";
- groups = "msp0txrx_a_1", "msp0tfstck_a_1";
- };
- default_msp0_cfg {
- pins =
- "GPIO12_AC4", /* TXD */
- "GPIO15_AC3", /* RXD */
- "GPIO13_AF3", /* TFS */
- "GPIO14_AE3"; /* TCK */
- ste,config = <&in_nopull>;
- };
- };
- };
-
- msp1 {
- msp1_default_mode: msp1_default {
- default_mux {
- function = "msp1";
- groups = "msp1txrx_a_1", "msp1_a_1";
- };
- default_cfg1 {
- pins = "GPIO33_AF2";
- ste,config = <&out_lo>;
- };
- default_cfg2 {
- pins =
- "GPIO34_AE1",
- "GPIO35_AE2",
- "GPIO36_AG2";
- ste,config = <&in_nopull>;
- };
-
- };
- };
-
- msp2 {
- msp2_default_mode: msp2_default {
- /* MSP2 usually used for HDMI audio */
- default_mux {
- function = "msp2";
- groups = "msp2_a_1";
- };
- default_cfg1 {
- pins =
- "GPIO193_AH27", /* TXD */
- "GPIO194_AF27", /* TCK */
- "GPIO195_AG28"; /* TFS */
- ste,config = <&in_pd>;
- };
- default_cfg2 {
- pins = "GPIO196_AG26"; /* RXD */
- ste,config = <&out_lo>;
- };
- };
- };
-
-
- musb {
- musb_default_mode: musb_default {
- default_mux {
- function = "usb";
- groups = "usb_a_1";
- };
- default_cfg1 {
- pins =
- "GPIO256_AF28", /* NXT */
- "GPIO258_AD29", /* XCLK */
- "GPIO259_AC29", /* DIR */
- "GPIO260_AD28", /* DAT7 */
- "GPIO261_AD26", /* DAT6 */
- "GPIO262_AE26", /* DAT5 */
- "GPIO263_AG29", /* DAT4 */
- "GPIO264_AE27", /* DAT3 */
- "GPIO265_AD27", /* DAT2 */
- "GPIO266_AC28", /* DAT1 */
- "GPIO267_AC27"; /* DAT0 */
- ste,config = <&in_nopull>;
- };
- default_cfg2 {
- pins = "GPIO257_AE29"; /* STP */
- ste,config = <&out_hi>;
- };
- };
-
- musb_sleep_mode: musb_sleep {
- sleep_cfg1 {
- pins =
- "GPIO256_AF28", /* NXT */
- "GPIO258_AD29", /* XCLK */
- "GPIO259_AC29"; /* DIR */
- ste,config = <&slpm_wkup_pdis_en>;
- };
- sleep_cfg2 {
- pins = "GPIO257_AE29"; /* STP */
- ste,config = <&slpm_out_hi_wkup_pdis>;
- };
- sleep_cfg3 {
- pins =
- "GPIO260_AD28", /* DAT7 */
- "GPIO261_AD26", /* DAT6 */
- "GPIO262_AE26", /* DAT5 */
- "GPIO263_AG29", /* DAT4 */
- "GPIO264_AE27", /* DAT3 */
- "GPIO265_AD27", /* DAT2 */
- "GPIO266_AC28", /* DAT1 */
- "GPIO267_AC27"; /* DAT0 */
- ste,config = <&slpm_in_wkup_pdis_en>;
- };
- };
- };
-
mcde {
lcd_default_mode: lcd_default {
default_mux1 {
diff --git a/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi
new file mode 100644
index 000000000000..e024520f4d47
--- /dev/null
+++ b/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Device Tree for the TVK1281618 R2 UIB
+ */
+
+#include "ste-href-tvk1281618.dtsi"
+
+/ {
+ soc {
+ i2c@80128000 {
+ lsm303dlh@18 {
+ /* Accelerometer */
+ compatible = "st,lsm303dlh-accel";
+ st,drdy-int-pin = <1>;
+ drive-open-drain;
+ reg = <0x18>;
+ vdd-supply = <&ab8500_ldo_aux1_reg>;
+ vddio-supply = <&db8500_vsmps2_reg>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&accel_tvk_mode>;
+ /*
+ * These interrupts cannot be used: the other component
+ * ST-Micro L3D4200D gyro that is connected to the same lines
+ * cannot set its DRDY line to open drain, so it cannot be
+ * shared with other peripherals. The should be defined for
+ * the falling edge if they could be wired together.
+ *
+ * interrupts-extended =
+ * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>,
+ * <&gpio2 19 IRQ_TYPE_EDGE_FALLING>;
+ */
+ };
+ lsm303dlh@1e {
+ /* Magnetometer */
+ compatible = "st,lsm303dlh-magn";
+ reg = <0x1e>;
+ vdd-supply = <&ab8500_ldo_aux1_reg>;
+ vddio-supply = <&db8500_vsmps2_reg>;
+ /*
+ * These interrupts cannot be used: the other component
+ * ST-Micro L3D4200D gyro that is connected to the same lines
+ * cannot set its DRDY line to open drain, so it cannot be
+ * shared with other peripherals. The should be defined for
+ * the falling edge if they could be wired together.
+ *
+ * interrupts-extended =
+ * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>,
+ * <&gpio2 19 IRQ_TYPE_EDGE_FALLING>;
+ */
+ };
+ lis331dl@1c {
+ /* Accelerometer */
+ compatible = "st,lis331dl-accel";
+ st,drdy-int-pin = <1>;
+ reg = <0x1c>;
+ vdd-supply = <&ab8500_ldo_aux1_reg>;
+ vddio-supply = <&db8500_vsmps2_reg>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&accel_tvk_mode>;
+ interrupt-parent = <&gpio2>;
+ /* INT2 would need to be open drain */
+ interrupts = <18 IRQ_TYPE_EDGE_RISING>,
+ <19 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+ mcde@a0350000 {
+ status = "okay";
+
+ dsi@a0351000 {
+ panel {
+ compatible = "samsung,s6d16d0";
+ reg = <0>;
+ vdd1-supply = <&ab8500_ldo_aux1_reg>;
+ reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi
new file mode 100644
index 000000000000..cb3677f0a1cb
--- /dev/null
+++ b/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Device Tree for the TVK1281618 R2 UIB
+ */
+
+#include "ste-href-tvk1281618.dtsi"
+
+/ {
+ soc {
+ i2c@80128000 {
+ /* Marked:
+ * 129
+ * M35
+ * L3GD20
+ */
+ l3gd20@6a {
+ /* Gyroscope */
+ compatible = "st,l3gd20";
+ status = "disabled";
+ st,drdy-int-pin = <1>;
+ drive-open-drain;
+ reg = <0x6a>; // 0x6a or 0x6b
+ vdd-supply = <&ab8500_ldo_aux1_reg>;
+ vddio-supply = <&db8500_vsmps2_reg>;
+ };
+ /*
+ * Marked:
+ * 2122
+ * C3H
+ * DQEEE
+ * LIS3DH?
+ */
+ lis3dh@18 {
+ /* Accelerometer */
+ compatible = "st,lis3dh-accel";
+ st,drdy-int-pin = <1>;
+ reg = <0x18>;
+ vdd-supply = <&ab8500_ldo_aux1_reg>;
+ vddio-supply = <&db8500_vsmps2_reg>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&accel_tvk_mode>;
+ };
+ };
+
+ mcde@a0350000 {
+ status = "okay";
+
+ dsi@a0351000 {
+ panel {
+ compatible = "sony,acx424akp";
+ reg = <0>;
+ vddi-supply = <&ab8500_ldo_aux1_reg>;
+ reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
index 3bafd26b4824..e1dbfae22595 100644
--- a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
+++ b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
@@ -2,7 +2,7 @@
/*
* Copyright 2012 ST-Ericsson AB
*
- * Device Tree for the TVK1281618 UIB
+ * Device Tree for the TVK1281618 family of UIBs
*/
#include <dt-bindings/interrupt-controller/irq.h>
@@ -81,62 +81,8 @@
};
};
};
- /* Sensors mounted on this board variant */
+ /* Sensors mounted on all board variants */
i2c@80128000 {
- lsm303dlh@18 {
- /* Accelerometer */
- compatible = "st,lsm303dlh-accel";
- st,drdy-int-pin = <1>;
- drive-open-drain;
- reg = <0x18>;
- vdd-supply = <&ab8500_ldo_aux1_reg>;
- vddio-supply = <&db8500_vsmps2_reg>;
- pinctrl-names = "default";
- pinctrl-0 = <&accel_tvk_mode>;
- /*
- * These interrupts cannot be used: the other component
- * ST-Micro L3D4200D gyro that is connected to the same lines
- * cannot set its DRDY line to open drain, so it cannot be
- * shared with other peripherals. The should be defined for
- * the falling edge if they could be wired together.
- *
- * interrupts-extended =
- * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>,
- * <&gpio2 19 IRQ_TYPE_EDGE_FALLING>;
- */
- };
- lsm303dlh@1e {
- /* Magnetometer */
- compatible = "st,lsm303dlh-magn";
- reg = <0x1e>;
- vdd-supply = <&ab8500_ldo_aux1_reg>;
- vddio-supply = <&db8500_vsmps2_reg>;
- /*
- * These interrupts cannot be used: the other component
- * ST-Micro L3D4200D gyro that is connected to the same lines
- * cannot set its DRDY line to open drain, so it cannot be
- * shared with other peripherals. The should be defined for
- * the falling edge if they could be wired together.
- *
- * interrupts-extended =
- * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>,
- * <&gpio2 19 IRQ_TYPE_EDGE_FALLING>;
- */
- };
- lis331dl@1c {
- /* Accelerometer */
- compatible = "st,lis331dl-accel";
- st,drdy-int-pin = <1>;
- reg = <0x1c>;
- vdd-supply = <&ab8500_ldo_aux1_reg>;
- vddio-supply = <&db8500_vsmps2_reg>;
- pinctrl-names = "default";
- pinctrl-0 = <&accel_tvk_mode>;
- interrupt-parent = <&gpio2>;
- /* INT2 would need to be open drain */
- interrupts = <18 IRQ_TYPE_EDGE_RISING>,
- <19 IRQ_TYPE_EDGE_RISING>;
- };
ak8974@f {
/* Magnetometer */
compatible = "asahi-kasei,ak8974";
@@ -268,18 +214,5 @@
};
};
};
-
- mcde@a0350000 {
- status = "okay";
-
- dsi@a0351000 {
- panel {
- compatible = "samsung,s6d16d0";
- reg = <0>;
- vdd1-supply = <&ab8500_ldo_aux1_reg>;
- reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
- };
- };
- };
};
};
diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi
index 4f6acbd8c040..33e3b0b3c53d 100644
--- a/arch/arm/boot/dts/ste-href.dtsi
+++ b/arch/arm/boot/dts/ste-href.dtsi
@@ -4,7 +4,6 @@
*/
#include <dt-bindings/interrupt-controller/irq.h>
-#include "ste-dbx5x0.dtsi"
#include "ste-href-family-pinctrl.dtsi"
/ {
@@ -16,41 +15,44 @@
soc {
uart@80120000 {
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&uart0_default_mode>;
- pinctrl-1 = <&uart0_sleep_mode>;
+ pinctrl-0 = <&u0_a_1_default>;
+ pinctrl-1 = <&u0_a_1_sleep>;
status = "okay";
};
/* This UART is unused and thus left disabled */
uart@80121000 {
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&uart1_default_mode>;
- pinctrl-1 = <&uart1_sleep_mode>;
+ pinctrl-0 = <&u1rxtx_a_1_default>;
+ pinctrl-1 = <&u1rxtx_a_1_sleep>;
};
uart@80007000 {
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&uart2_default_mode>;
- pinctrl-1 = <&uart2_sleep_mode>;
+ pinctrl-0 = <&u2rxtx_c_1_default>;
+ pinctrl-1 = <&u2rxtx_c_1_sleep>;
status = "okay";
};
i2c@80004000 {
pinctrl-names = "default","sleep";
- pinctrl-0 = <&i2c0_default_mode>;
- pinctrl-1 = <&i2c0_sleep_mode>;
+ pinctrl-0 = <&i2c0_a_1_default>;
+ pinctrl-1 = <&i2c0_a_1_sleep>;
+ status = "okay";
};
i2c@80122000 {
pinctrl-names = "default","sleep";
- pinctrl-0 = <&i2c1_default_mode>;
- pinctrl-1 = <&i2c1_sleep_mode>;
+ pinctrl-0 = <&i2c1_b_2_default>;
+ pinctrl-1 = <&i2c1_b_2_sleep>;
+ status = "okay";
};
i2c@80128000 {
pinctrl-names = "default","sleep";
- pinctrl-0 = <&i2c2_default_mode>;
- pinctrl-1 = <&i2c2_sleep_mode>;
+ pinctrl-0 = <&i2c2_b_2_default>;
+ pinctrl-1 = <&i2c2_b_2_sleep>;
+ status = "okay";
lp5521@33 {
compatible = "national,lp5521";
reg = <0x33>;
@@ -96,8 +98,9 @@
i2c@80110000 {
pinctrl-names = "default","sleep";
- pinctrl-0 = <&i2c3_default_mode>;
- pinctrl-1 = <&i2c3_sleep_mode>;
+ pinctrl-0 = <&i2c3_c_2_default>;
+ pinctrl-1 = <&i2c3_c_2_sleep>;
+ status = "okay";
};
/* ST6G3244ME level translator for 1.8/2.9 V */
@@ -132,8 +135,8 @@
vmmc-supply = <&ab8500_ldo_aux3_reg>;
vqmmc-supply = <&vmmci>;
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sdi0_default_mode>;
- pinctrl-1 = <&sdi0_sleep_mode>;
+ pinctrl-0 = <&mc0_a_1_default &sdi0_default_mode>;
+ pinctrl-1 = <&mc0_a_1_sleep>;
status = "okay";
};
@@ -145,8 +148,8 @@
bus-width = <4>;
non-removable;
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sdi1_default_mode>;
- pinctrl-1 = <&sdi1_sleep_mode>;
+ pinctrl-0 = <&mc1_a_1_default>;
+ pinctrl-1 = <&mc1_a_1_sleep>;
status = "okay";
};
@@ -160,8 +163,8 @@
non-removable;
vmmc-supply = <&db8500_vsmps2_reg>;
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sdi2_default_mode>;
- pinctrl-1 = <&sdi2_sleep_mode>;
+ pinctrl-0 = <&mc2_a_1_default>;
+ pinctrl-1 = <&mc2_a_1_sleep>;
status = "okay";
};
@@ -175,27 +178,27 @@
non-removable;
vmmc-supply = <&ab8500_ldo_aux2_reg>;
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sdi4_default_mode>;
- pinctrl-1 = <&sdi4_sleep_mode>;
+ pinctrl-0 = <&mc4_a_1_default>;
+ pinctrl-1 = <&mc4_a_1_sleep>;
status = "okay";
};
msp0: msp@80123000 {
pinctrl-names = "default";
- pinctrl-0 = <&msp0_default_mode>;
+ pinctrl-0 = <&msp0txrxtfstck_a_1_default>;
status = "okay";
};
msp1: msp@80124000 {
pinctrl-names = "default";
- pinctrl-0 = <&msp1_default_mode>;
+ pinctrl-0 = <&msp1txrx_a_1_default>;
status = "okay";
};
msp2: msp@80117000 {
pinctrl-names = "default";
- pinctrl-0 = <&msp2_default_mode>;
+ pinctrl-0 = <&msp2_a_1_default>;
};
msp3: msp@80125000 {
@@ -209,8 +212,8 @@
ab8500_usb {
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&musb_default_mode>;
- pinctrl-1 = <&musb_sleep_mode>;
+ pinctrl-0 = <&usb_a_1_default>;
+ pinctrl-1 = <&usb_a_1_sleep>;
};
ab8500-regulators {
@@ -257,6 +260,14 @@
};
};
+ pinctrl {
+ sdi0 {
+ sdi0_default_mode: sdi0_default {
+ /* Some boards set additional settings here */
+ };
+ };
+ };
+
mcde@a0350000 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&lcd_default_mode>;
diff --git a/arch/arm/boot/dts/ste-href520-tvk.dts b/arch/arm/boot/dts/ste-href520-tvk.dts
new file mode 100644
index 000000000000..f8c0c1e6aa04
--- /dev/null
+++ b/arch/arm/boot/dts/ste-href520-tvk.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Device Tree for the HREF520 version with the TVK1281618 UIB
+ */
+
+/dts-v1/;
+#include "ste-db8520.dtsi"
+#include "ste-hrefv60plus.dtsi"
+#include "ste-href-tvk1281618-r3.dtsi"
+
+/ {
+ model = "ST-Ericsson HREF520 and TVK1281618 UIB";
+ compatible = "st-ericsson,href520", "st-ericsson,u8500";
+
+ soc {
+ vmmci: regulator-gpio {
+ gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+ enable-gpio = <&gpio2 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/ste-hrefprev60-stuib.dts b/arch/arm/boot/dts/ste-hrefprev60-stuib.dts
index b78be5f4c212..8ce6b723abf2 100644
--- a/arch/arm/boot/dts/ste-hrefprev60-stuib.dts
+++ b/arch/arm/boot/dts/ste-hrefprev60-stuib.dts
@@ -4,8 +4,7 @@
*/
/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
+#include "ste-db8500.dtsi"
#include "ste-hrefprev60.dtsi"
#include "ste-href-stuib.dtsi"
@@ -13,13 +12,6 @@
model = "ST-Ericsson HREF (pre-v60) and ST UIB";
compatible = "st-ericsson,mop500", "st-ericsson,u8500";
- /* This stablilizes the serial port enumeration */
- aliases {
- serial0 = &ux500_serial0;
- serial1 = &ux500_serial1;
- serial2 = &ux500_serial2;
- };
-
soc {
/* Reset line for the BU21013 touchscreen */
i2c@80110000 {
diff --git a/arch/arm/boot/dts/ste-hrefprev60-tvk.dts b/arch/arm/boot/dts/ste-hrefprev60-tvk.dts
index 60eed262d920..142f5475521f 100644
--- a/arch/arm/boot/dts/ste-hrefprev60-tvk.dts
+++ b/arch/arm/boot/dts/ste-hrefprev60-tvk.dts
@@ -4,17 +4,11 @@
*/
/dts-v1/;
+#include "ste-db8500.dtsi"
#include "ste-hrefprev60.dtsi"
-#include "ste-href-tvk1281618.dtsi"
+#include "ste-href-tvk1281618-r2.dtsi"
/ {
model = "ST-Ericsson HREF (pre-v60) and TVK1281618 UIB";
compatible = "st-ericsson,mop500", "st-ericsson,u8500";
-
- /* This stablilizes the serial port enumeration */
- aliases {
- serial0 = &ux500_serial0;
- serial1 = &ux500_serial1;
- serial2 = &ux500_serial2;
- };
};
diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi
index a036defdf164..115495de8612 100644
--- a/arch/arm/boot/dts/ste-hrefprev60.dtsi
+++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi
@@ -5,7 +5,6 @@
* Device Tree for the HREF+ prior to the v60 variant.
*/
-#include "ste-dbx5x0.dtsi"
#include "ste-href-ab8500.dtsi"
#include "ste-href.dtsi"
@@ -58,6 +57,7 @@
*/
pinctrl-names = "default";
pinctrl-0 = <&ssp0_hrefprev60_mode>;
+ status = "okay";
};
// External Micro SD slot
diff --git a/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts b/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts
index 9be513aad549..1316886e6bcb 100644
--- a/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts
+++ b/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts
@@ -6,8 +6,7 @@
*/
/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
+#include "ste-db8500.dtsi"
#include "ste-hrefv60plus.dtsi"
#include "ste-href-stuib.dtsi"
@@ -15,13 +14,6 @@
model = "ST-Ericsson HREF (v60+) and ST UIB";
compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500";
- /* This stablilizes the serial port enumeration */
- aliases {
- serial0 = &ux500_serial0;
- serial1 = &ux500_serial1;
- serial2 = &ux500_serial2;
- };
-
soc {
/* Reset line for the BU21013 touchscreen */
i2c@80110000 {
diff --git a/arch/arm/boot/dts/ste-hrefv60plus-tvk.dts b/arch/arm/boot/dts/ste-hrefv60plus-tvk.dts
index 73ea3100f186..5d4b8245f02c 100644
--- a/arch/arm/boot/dts/ste-hrefv60plus-tvk.dts
+++ b/arch/arm/boot/dts/ste-hrefv60plus-tvk.dts
@@ -6,17 +6,11 @@
*/
/dts-v1/;
+#include "ste-db8500.dtsi"
#include "ste-hrefv60plus.dtsi"
-#include "ste-href-tvk1281618.dtsi"
+#include "ste-href-tvk1281618-r2.dtsi"
/ {
model = "ST-Ericsson HREF (v60+) and TVK1281618 UIB";
compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500";
-
- /* This stablilizes the serial port enumeration */
- aliases {
- serial0 = &ux500_serial0;
- serial1 = &ux500_serial1;
- serial2 = &ux500_serial2;
- };
};
diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
index aece8eb2924f..05b4fbbba57f 100644
--- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi
+++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
@@ -3,7 +3,6 @@
* Copyright 2012 ST-Ericsson AB
*/
-#include "ste-dbx5x0.dtsi"
#include "ste-href-ab8500.dtsi"
#include "ste-href.dtsi"
diff --git a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi
index 5673a1113aef..bfdb5d9a014f 100644
--- a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi
@@ -25,6 +25,11 @@
ste,output = <OUTPUT_LOW>;
};
+ gpio_in_nopull: gpio_input_nopull {
+ ste,gpio = <GPIOMODE_ENABLED>;
+ ste,input = <INPUT_NOPULL>;
+ };
+
gpio_in_pu: gpio_input_pull_up {
ste,gpio = <GPIOMODE_ENABLED>;
ste,input = <INPUT_PULLUP>;
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index efbc4467b8b7..be90e73c923e 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -4,7 +4,7 @@
*/
/dts-v1/;
-#include "ste-dbx5x0.dtsi"
+#include "ste-db8500.dtsi"
#include "ste-href-ab8500.dtsi"
#include "ste-href-family-pinctrl.dtsi"
@@ -12,13 +12,6 @@
model = "Calao Systems Snowball platform with device tree";
compatible = "calaosystems,snowball-a9500", "st-ericsson,u9500";
- /* This stablilizes the serial port enumeration */
- aliases {
- serial0 = &ux500_serial0;
- serial1 = &ux500_serial1;
- serial2 = &ux500_serial2;
- };
-
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>;
@@ -156,19 +149,19 @@
msp0: msp@80123000 {
pinctrl-names = "default";
- pinctrl-0 = <&msp0_default_mode>;
+ pinctrl-0 = <&msp0txrxtfstck_a_1_default>;
status = "okay";
};
msp1: msp@80124000 {
pinctrl-names = "default";
- pinctrl-0 = <&msp1_default_mode>;
+ pinctrl-0 = <&msp1txrx_a_1_default>;
status = "okay";
};
msp2: msp@80117000 {
pinctrl-names = "default";
- pinctrl-0 = <&msp2_default_mode>;
+ pinctrl-0 = <&msp2_a_1_default>;
};
msp3: msp@80125000 {
@@ -238,8 +231,8 @@
vmmc-supply = <&ab8500_ldo_aux3_reg>;
vqmmc-supply = <&vmmci>;
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sdi0_default_mode>;
- pinctrl-1 = <&sdi0_sleep_mode>;
+ pinctrl-0 = <&mc0_a_1_default &sdi0_default_mode>;
+ pinctrl-1 = <&mc0_a_1_sleep>;
/* GPIO218 MMC_CD */
cd-gpios = <&gpio6 26 GPIO_ACTIVE_LOW>;
@@ -253,8 +246,8 @@
max-frequency = <100000000>;
bus-width = <4>;
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sdi1_default_mode>;
- pinctrl-1 = <&sdi1_sleep_mode>;
+ pinctrl-0 = <&mc1_a_1_default>;
+ pinctrl-1 = <&mc1_a_1_sleep>;
status = "okay";
};
@@ -263,7 +256,7 @@
sdi2_per3@80005000 {
arm,primecell-periphid = <0x10480180>;
pinctrl-names = "default";
- pinctrl-0 = <&sdi2_sleep_mode>;
+ pinctrl-0 = <&mc2_a_1_sleep>;
status = "okay";
};
@@ -276,49 +269,52 @@
cap-mmc-highspeed;
vmmc-supply = <&ab8500_ldo_aux2_reg>;
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sdi4_default_mode>;
- pinctrl-1 = <&sdi4_sleep_mode>;
+ pinctrl-0 = <&mc4_a_1_default>;
+ pinctrl-1 = <&mc4_a_1_sleep>;
status = "okay";
};
uart@80120000 {
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&uart0_default_mode>;
- pinctrl-1 = <&uart0_sleep_mode>;
+ pinctrl-0 = <&u0_a_1_default>;
+ pinctrl-1 = <&u0_a_1_sleep>;
status = "okay";
};
/* This UART is unused and thus left disabled */
uart@80121000 {
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&uart1_default_mode>;
- pinctrl-1 = <&uart1_sleep_mode>;
+ pinctrl-0 = <&u1rxtx_a_1_default>;
+ pinctrl-1 = <&u1rxtx_a_1_sleep>;
};
uart@80007000 {
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&uart2_default_mode>;
- pinctrl-1 = <&uart2_sleep_mode>;
+ pinctrl-0 = <&u2rxtx_c_1_default>;
+ pinctrl-1 = <&u2rxtx_c_1_sleep>;
status = "okay";
};
i2c@80004000 {
pinctrl-names = "default","sleep";
- pinctrl-0 = <&i2c0_default_mode>;
- pinctrl-1 = <&i2c0_sleep_mode>;
+ pinctrl-0 = <&i2c0_a_1_default>;
+ pinctrl-1 = <&i2c0_a_1_sleep>;
+ status = "okay";
};
i2c@80122000 {
pinctrl-names = "default","sleep";
- pinctrl-0 = <&i2c1_default_mode>;
- pinctrl-1 = <&i2c1_sleep_mode>;
+ pinctrl-0 = <&i2c1_b_2_default>;
+ pinctrl-1 = <&i2c1_b_2_sleep>;
+ status = "okay";
};
i2c@80128000 {
pinctrl-names = "default","sleep";
- pinctrl-0 = <&i2c2_default_mode>;
- pinctrl-1 = <&i2c2_sleep_mode>;
+ pinctrl-0 = <&i2c2_b_2_default>;
+ pinctrl-1 = <&i2c2_b_2_sleep>;
+ status = "okay";
lsm303dlh@18 {
/* Accelerometer */
compatible = "st,lsm303dlh-accel";
@@ -367,20 +363,18 @@
i2c@80110000 {
pinctrl-names = "default","sleep";
- pinctrl-0 = <&i2c3_default_mode>;
- pinctrl-1 = <&i2c3_sleep_mode>;
+ pinctrl-0 = <&i2c3_c_2_default>;
+ pinctrl-1 = <&i2c3_c_2_sleep>;
+ status = "okay";
};
spi@80002000 {
pinctrl-names = "default";
pinctrl-0 = <&ssp0_snowball_mode>;
+ status = "okay";
};
prcmu@80157000 {
- cpufreq {
- status = "okay";
- };
-
ab8500 {
ab8500-gpio {
/*
@@ -406,8 +400,8 @@
ab8500_usb {
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&musb_default_mode>;
- pinctrl-1 = <&musb_sleep_mode>;
+ pinctrl-0 = <&usb_a_1_default>;
+ pinctrl-1 = <&usb_a_1_sleep>;
};
ext_regulators: ab8500-ext-regulators {
diff --git a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts
new file mode 100644
index 000000000000..313f0ab16866
--- /dev/null
+++ b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts
@@ -0,0 +1,455 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/dts-v1/;
+
+#include "ste-db8500.dtsi"
+#include "ste-ab8505.dtsi"
+#include "ste-dbx5x0-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/*
+ * Note: This device tree cannot be booted directly with the Samsung bootloader.
+ * You need an intermediate, device-tree compatible bootloader
+ * that locks the L2 cache. Otherwise the kernel will crash after decompression.
+ *
+ * There is a port of (mainline) U-Boot, see
+ * https://wiki.postmarketos.org/wiki/ST-Ericsson_NovaThor_U8500#U-Boot
+ */
+/ {
+ model = "Samsung Galaxy S III mini (GT-I8190)";
+ compatible = "samsung,golden", "st-ericsson,u8500";
+
+ chosen {
+ stdout-path = &serial2;
+ };
+
+ soc {
+ /* External Micro SD card slot */
+ sdi0_per1@80126000 {
+ status = "okay";
+
+ arm,primecell-periphid = <0x10480180>;
+ max-frequency = <100000000>;
+ bus-width = <4>;
+
+ non-removable;
+ /*
+ * Unfortunately, there is no way to enable the UHS
+ * modes due to a limitation of the SD level translator:
+ * It will either translate to 2.9V or disconnect the
+ * DATA lines, so switching to 1.8V signal voltage fails.
+ */
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ st,sig-pin-fbclk;
+ full-pwr-cycle;
+
+ vmmc-supply = <&ab8500_ldo_aux3_reg>;
+ vqmmc-supply = <&sd_level_translator>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mc0_a_2_default>;
+ pinctrl-1 = <&mc0_a_2_sleep>;
+ };
+
+ /* WLAN SDIO */
+ sdi1_per2@80118000 {
+ status = "okay";
+
+ arm,primecell-periphid = <0x10480180>;
+ max-frequency = <50000000>;
+ bus-width = <4>;
+
+ non-removable;
+ cap-sd-highspeed;
+
+ vmmc-supply = <&wl_reg_on>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mc1_a_2_default>;
+ pinctrl-1 = <&mc1_a_2_sleep>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+
+ /* GPIO216 (WLAN_HOST_WAKE) */
+ interrupt-parent = <&gpio6>;
+ interrupts = <24 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-names = "host-wake";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_default>;
+ };
+ };
+
+ /* eMMC */
+ sdi2_per3@80005000 {
+ status = "okay";
+
+ arm,primecell-periphid = <0x10480180>;
+ max-frequency = <100000000>;
+ bus-width = <8>;
+
+ non-removable;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+
+ vmmc-supply = <&vmem_3v3>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mc2_a_1_default>;
+ pinctrl-1 = <&mc2_a_1_sleep>;
+ };
+
+ /* BT UART */
+ uart@80120000 {
+ status = "okay";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&u0_a_1_default>;
+ pinctrl-1 = <&u0_a_1_sleep>;
+
+ bluetooth {
+ compatible = "brcm,bcm4330-bt";
+ /* GPIO222 (BT_VREG_ON) */
+ shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>;
+ /* GPIO199 (BT_WAKE) */
+ device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
+ /* GPIO97 (BT_HOST_WAKE) */
+ host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&bluetooth_default>;
+ };
+ };
+
+ /* GPF UART */
+ uart@80121000 {
+ status = "okay";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>;
+ pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>;
+ };
+
+ /* Debugging console UART */
+ uart@80007000 {
+ status = "okay";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&u2rxtx_c_1_default>;
+ pinctrl-1 = <&u2rxtx_c_1_sleep>;
+ };
+
+ i2c@80128000 {
+ status = "okay";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c2_b_2_default>;
+ pinctrl-1 = <&i2c2_b_2_sleep>;
+
+ imu@68 {
+ compatible = "invensense,mpu6050";
+ reg = <0x68>;
+
+ /* GPIO206 (ACC_INT) */
+ interrupt-parent = <&gpio6>;
+ interrupts = <14 IRQ_TYPE_EDGE_RISING>;
+
+ mount-matrix = "0", "1", "0",
+ "-1", "0", "0",
+ "0", "0", "1";
+
+ vdd-supply = <&ab8500_ldo_aux1_reg>;
+ vddio-supply = <&ab8500_ldo_aux8_reg>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&imu_default>;
+ };
+ };
+
+ i2c@80110000 {
+ status = "okay";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c3_c_2_default>;
+ pinctrl-1 = <&i2c3_c_2_sleep>;
+
+ touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ reg = <0x4a>;
+
+ /* GPIO218 (TSP_INT_1V8) */
+ interrupt-parent = <&gpio6>;
+ interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tsp_default>;
+ };
+ };
+
+ prcmu@80157000 {
+ ab8505 {
+ ab8500_usb {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&usb_a_1_default>;
+ pinctrl-1 = <&usb_a_1_sleep>;
+ };
+
+ ab8505-regulators {
+ ab8500_ldo_aux1 {
+ regulator-name = "sensor_3v";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ ab8500_ldo_aux2 {
+ regulator-name = "vreg_tsp_a3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on; /* FIXME */
+ };
+
+ ab8500_ldo_aux3 {
+ regulator-name = "vdd_tf_2v91";
+ };
+
+ ab8500_ldo_aux4 {
+ regulator-name = "key_led_3.3v";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ab8500_ldo_aux5 {
+ regulator-name = "vreg_tsp_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on; /* FIXME */
+ };
+
+ ab8500_ldo_aux6 {
+ regulator-name = "touch_key_2.2v";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ };
+
+ ab8500_ldo_aux8 {
+ regulator-name = "sensor_1v8";
+ };
+ };
+ };
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_default>;
+
+ label = "GPIO Buttons";
+
+ volume-up {
+ label = "Volume Up";
+ /* GPIO67 (VOL_UP) */
+ gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+
+ volume-down {
+ label = "Volume Down";
+ /* GPIO92 (VOL_DOWN) */
+ gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+
+ home {
+ label = "Home";
+ /* GPIO91 (HOME_KEY) */
+ gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_HOMEPAGE>;
+ };
+ };
+
+ vibrator {
+ compatible = "gpio-vibrator";
+ /* GPIO195 (MOT_EN) */
+ enable-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&vibrator_default>;
+ };
+
+ /* External LDO for eMMC */
+ vmem_3v3: regulator-vmem {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vmem_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+
+ startup-delay-us = <200>;
+
+ /* GPIO223 (MEM_LDO_EN) */
+ gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&mem_ldo_default>;
+ };
+
+ /* TI TXS0206-29 level translator for 2.9 V */
+ sd_level_translator: regulator-sd-level-translator {
+ compatible = "regulator-fixed";
+
+ regulator-name = "sd-level-translator";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+
+ startup-delay-us = <200>;
+
+ /* GPIO87 (TXS0206-29_EN) */
+ gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd_level_translator_default>;
+ };
+
+ /*
+ * WL_REG_ON takes WLAN out of reset and enables the internal regulators.
+ * The voltage specified here is only used to determine the OCR mask,
+ * the BCM chip is actually connected directly to VBAT.
+ */
+ wl_reg_on: regulator-wl-reg-on {
+ compatible = "regulator-fixed";
+
+ regulator-name = "wl-reg-on";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+
+ startup-delay-us = <100000>;
+
+ /* GPIO215 (WLAN_EN) */
+ gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_en_default>;
+ };
+};
+
+&pinctrl {
+ gpio-keys {
+ gpio_keys_default: gpio_keys_default {
+ golden_cfg1 {
+ pins = "GPIO67", /* VOL_UP */
+ "GPIO91", /* HOME_KEY */
+ "GPIO92"; /* VOL_DOWN */
+ ste,config = <&gpio_in_pu>;
+ };
+ };
+ };
+
+ sdi0 {
+ sd_level_translator_default: sd_level_translator_default {
+ golden_cfg1 {
+ pins = "GPIO87_B3"; /* TXS0206-29_EN */
+ ste,config = <&gpio_out_lo>;
+ };
+ };
+ };
+
+ sdi2 {
+ mem_ldo_default: mem_ldo_default {
+ golden_cfg1 {
+ pins = "GPIO223_AH9"; /* MEM_LDO_EN */
+ ste,config = <&gpio_out_hi>;
+ };
+ };
+ };
+
+ imu {
+ imu_default: imu_default {
+ golden_cfg1 {
+ pins = "GPIO206_AG24"; /* ACC_INT */
+ ste,config = <&gpio_in_pd>;
+ };
+ };
+ };
+
+ tsp {
+ tsp_default: tsp_default {
+ golden_cfg1 {
+ pins = "GPIO218_AH11"; /* TSP_INT_1V8 */
+ ste,config = <&gpio_in_nopull>;
+ };
+ };
+ };
+
+ wlan {
+ wlan_default: wlan_default {
+ golden_cfg1 {
+ pins = "GPIO216_AG12"; /* WLAN_HOST_WAKE */
+ ste,config = <&gpio_in_pd>;
+ };
+ };
+
+ wlan_en_default: wlan_en_default {
+ golden_cfg1 {
+ pins = "GPIO215_AH13"; /* WLAN_EN */
+ ste,config = <&gpio_out_lo>;
+ };
+ };
+ };
+
+ bluetooth {
+ bluetooth_default: bluetooth_default {
+ golden_cfg1 {
+ pins = "GPIO199_AH23", /* BT_WAKE */
+ "GPIO222_AJ9"; /* BT_VREG_ON */
+ ste,config = <&gpio_out_lo>;
+ };
+ golden_cfg2 {
+ pins = "GPIO97_D9"; /* BT_HOST_WAKE */
+ ste,config = <&gpio_in_nopull>;
+ };
+ };
+ };
+
+ vibrator {
+ vibrator_default: vibrator_default {
+ golden_cfg1 {
+ pins = "GPIO195_AG28"; /* MOT_EN */
+ ste,config = <&gpio_out_lo>;
+ };
+ };
+ };
+};
+
+&ab8505_gpio {
+ /* Hog a few default settings */
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_default>;
+
+ gpio {
+ gpio_default: gpio_default {
+ golden_mux {
+ /* Change unused pins to GPIO mode */
+ function = "gpio";
+ groups = "gpio3_a_1", /* default: SysClkReq4 */
+ "gpio14_a_1"; /* default: PWMOut1 */
+ };
+ golden_cfg1 {
+ pins = "GPIO11_B17", "GPIO13_D17", "GPIO50_L4";
+ bias-disable;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 58288aa53fee..c27fa355e5ab 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -95,6 +95,13 @@
regulator-max-microvolt = <3300000>;
};
+ vdd_panel: vdd-panel {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_panel";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
leds {
compatible = "gpio-leds";
green {
@@ -138,6 +145,7 @@
panel_rgb: panel-rgb {
compatible = "ampire,am-480272h3tmqw-t01h";
+ power-supply = <&vdd_panel>;
status = "okay";
port {
panel_in_rgb: endpoint {
diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
index 35202896c093..392fa143ce07 100644
--- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
@@ -163,7 +163,7 @@
st,bank-name = "GPIOK";
};
- usart1_pins_a: usart1@0 {
+ usart1_pins_a: usart1-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
bias-disable;
@@ -176,7 +176,7 @@
};
};
- usart3_pins_a: usart3@0 {
+ usart3_pins_a: usart3-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
bias-disable;
@@ -189,7 +189,7 @@
};
};
- usbotg_fs_pins_a: usbotg_fs@0 {
+ usbotg_fs_pins_a: usbotg-fs-0 {
pins {
pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
<STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
@@ -200,7 +200,7 @@
};
};
- usbotg_fs_pins_b: usbotg_fs@1 {
+ usbotg_fs_pins_b: usbotg-fs-1 {
pins {
pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */
<STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */
@@ -211,7 +211,7 @@
};
};
- usbotg_hs_pins_a: usbotg_hs@0 {
+ usbotg_hs_pins_a: usbotg-hs-0 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT*/
<STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
@@ -231,7 +231,7 @@
};
};
- ethernet_mii: mii@0 {
+ ethernet_mii: mii-0 {
pins {
pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */
<STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */
@@ -251,13 +251,13 @@
};
};
- adc3_in8_pin: adc@200 {
+ adc3_in8_pin: adc-200 {
pins {
pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
};
};
- pwm1_pins: pwm@1 {
+ pwm1_pins: pwm-1 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */
<STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */
@@ -265,14 +265,14 @@
};
};
- pwm3_pins: pwm@3 {
+ pwm3_pins: pwm-3 {
pins {
pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */
<STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
};
};
- i2c1_pins: i2c1@0 {
+ i2c1_pins: i2c1-0 {
pins {
pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */
<STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */
@@ -282,7 +282,7 @@
};
};
- ltdc_pins: ltdc@0 {
+ ltdc_pins: ltdc-0 {
pins {
pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
<STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
@@ -316,7 +316,7 @@
};
};
- dcmi_pins: dcmi@0 {
+ dcmi_pins: dcmi-0 {
pins {
pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */
<STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */
@@ -339,7 +339,7 @@
};
};
- sdio_pins: sdio_pins@0 {
+ sdio_pins: sdio-pins-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
@@ -352,7 +352,7 @@
};
};
- sdio_pins_od: sdio_pins_od@0 {
+ sdio_pins_od: sdio-pins-od-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 5c8a826b3195..d7770699feb5 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -80,7 +80,7 @@
};
soc {
- romem: nvmem@1fff7800 {
+ romem: efuse@1fff7800 {
compatible = "st,stm32f4-otp";
reg = <0x1fff7800 0x400>;
#address-cells = <1>;
@@ -318,7 +318,6 @@
compatible = "st,stm32-rtc";
reg = <0x40002800 0x400>;
clocks = <&rcc 1 CLK_RTC>;
- clock-names = "ck_rtc";
assigned-clocks = <&rcc 1 CLK_RTC>;
assigned-clock-parents = <&rcc 1 CLK_LSE>;
interrupt-parent = <&exti>;
@@ -789,7 +788,6 @@
rng: rng@50060800 {
compatible = "st,stm32-rng";
reg = <0x50060800 0x400>;
- interrupts = <80>;
clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
};
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts
index f3ce477b7bae..9397db0c43de 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -76,6 +76,13 @@
regulator-max-microvolt = <3300000>;
};
+ vdd_dsi: vdd-dsi {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_dsi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
soc {
dma-ranges = <0xc0000000 0x0 0x10000000>;
};
@@ -155,6 +162,7 @@
compatible = "orisetech,otm8009a";
reg = <0>; /* dsi virtual channel (0..3) */
reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
+ power-supply = <&vdd_dsi>;
status = "okay";
port {
diff --git a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi
index 9314128df185..fe4cfda72a47 100644
--- a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi
@@ -127,7 +127,7 @@
st,bank-name = "GPIOK";
};
- cec_pins_a: cec@0 {
+ cec_pins_a: cec-0 {
pins {
pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
slew-rate = <0>;
@@ -136,7 +136,7 @@
};
};
- usart1_pins_a: usart1@0 {
+ usart1_pins_a: usart1-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
bias-disable;
@@ -149,7 +149,7 @@
};
};
- usart1_pins_b: usart1@1 {
+ usart1_pins_b: usart1-1 {
pins1 {
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
bias-disable;
@@ -162,7 +162,7 @@
};
};
- i2c1_pins_b: i2c1@0 {
+ i2c1_pins_b: i2c1-0 {
pins {
pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
<STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
@@ -172,7 +172,7 @@
};
};
- usbotg_hs_pins_a: usbotg-hs@0 {
+ usbotg_hs_pins_a: usbotg-hs-0 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
<STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
@@ -192,7 +192,7 @@
};
};
- usbotg_hs_pins_b: usbotg-hs@1 {
+ usbotg_hs_pins_b: usbotg-hs-1 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
<STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
@@ -212,7 +212,7 @@
};
};
- usbotg_fs_pins_a: usbotg-fs@0 {
+ usbotg_fs_pins_a: usbotg-fs-0 {
pins {
pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
<STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
@@ -223,7 +223,7 @@
};
};
- sdio_pins_a: sdio_pins_a@0 {
+ sdio_pins_a: sdio-pins-a-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
@@ -236,7 +236,7 @@
};
};
- sdio_pins_od_a: sdio_pins_od_a@0 {
+ sdio_pins_od_a: sdio-pins-od-a-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
@@ -254,7 +254,7 @@
};
};
- sdio_pins_b: sdio_pins_b@0 {
+ sdio_pins_b: sdio-pins-b-0 {
pins {
pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
<STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
@@ -267,7 +267,7 @@
};
};
- sdio_pins_od_b: sdio_pins_od_b@0 {
+ sdio_pins_od_b: sdio-pins-od-b-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
<STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index d26f93f8b9c2..93c063796780 100644
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -300,7 +300,6 @@
compatible = "st,stm32-rtc";
reg = <0x40002800 0x400>;
clocks = <&rcc 1 CLK_RTC>;
- clock-names = "ck_rtc";
assigned-clocks = <&rcc 1 CLK_RTC>;
assigned-clock-parents = <&rcc 1 CLK_LSE>;
interrupt-parent = <&exti>;
@@ -587,7 +586,7 @@
assigned-clock-rates = <1000000>;
};
- dma1: dma@40026000 {
+ dma1: dma-controller@40026000 {
compatible = "st,stm32-dma";
reg = <0x40026000 0x400>;
interrupts = <11>,
@@ -603,7 +602,7 @@
status = "disabled";
};
- dma2: dma@40026400 {
+ dma2: dma-controller@40026400 {
compatible = "st,stm32-dma";
reg = <0x40026400 0x400>;
interrupts = <56>,
diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index c065266ee377..05eb02e6d083 100644
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -231,7 +231,7 @@
status = "disabled";
};
- dma1: dma@40020000 {
+ dma1: dma-controller@40020000 {
compatible = "st,stm32-dma";
reg = <0x40020000 0x400>;
interrupts = <11>,
@@ -249,7 +249,7 @@
status = "disabled";
};
- dma2: dma@40020400 {
+ dma2: dma-controller@40020400 {
compatible = "st,stm32-dma";
reg = <0x40020400 0x400>;
interrupts = <56>,
@@ -329,7 +329,7 @@
status = "disabled";
};
- mdma1: dma@52000000 {
+ mdma1: dma-controller@52000000 {
compatible = "st,stm32h7-mdma";
reg = <0x52000000 0x1000>;
interrupts = <122>;
diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
new file mode 100644
index 000000000000..0237d4ddaa92
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
@@ -0,0 +1,1092 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ */
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+
+&pinctrl {
+ adc1_in6_pins_a: adc1-in6 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+ };
+ };
+
+ adc12_ain_pins_a: adc12-ain-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */
+ <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
+ <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */
+ <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */
+ };
+ };
+
+ adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
+ <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
+ };
+ };
+
+ cec_pins_a: cec-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 15, AF4)>;
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ cec_pins_sleep_a: cec-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
+ };
+ };
+
+ cec_pins_b: cec-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 6, AF5)>;
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ cec_pins_sleep_b: cec-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
+ };
+ };
+
+ dac_ch1_pins_a: dac-ch1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
+ };
+ };
+
+ dac_ch2_pins_a: dac-ch2 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+ };
+ };
+
+ dcmi_pins_a: dcmi-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
+ <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
+ <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
+ <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */
+ <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
+ <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
+ <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
+ <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
+ <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
+ <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */
+ <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */
+ <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
+ bias-disable;
+ };
+ };
+
+ dcmi_sleep_pins_a: dcmi-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
+ <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
+ <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
+ <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */
+ <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
+ <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
+ <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
+ <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
+ <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
+ <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */
+ <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */
+ <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */
+ };
+ };
+
+ ethernet0_rgmii_pins_a: rgmii-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
+ <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
+ <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
+ bias-disable;
+ };
+ };
+
+ ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
+ <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
+ <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
+ <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
+ };
+ };
+
+ fmc_pins_a: fmc-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
+ <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
+ <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
+ <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
+ <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
+ <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
+ <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
+ <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
+ <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
+ <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
+ <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
+ <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
+ <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
+ bias-pull-up;
+ };
+ };
+
+ fmc_sleep_pins_a: fmc-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
+ <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
+ <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */
+ <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */
+ <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
+ <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
+ <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
+ <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
+ <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
+ <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
+ <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
+ <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
+ <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */
+ <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
+ };
+ };
+
+ i2c1_pins_a: i2c1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
+ <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c1_pins_sleep_a: i2c1-1 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
+ <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
+ };
+ };
+
+ i2c1_pins_b: i2c1-2 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
+ <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c1_pins_sleep_b: i2c1-3 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */
+ <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
+ };
+ };
+
+ i2c2_pins_a: i2c2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
+ <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c2_pins_sleep_a: i2c2-1 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
+ <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
+ };
+ };
+
+ i2c2_pins_b1: i2c2-2 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c2_pins_sleep_b1: i2c2-3 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
+ };
+ };
+
+ i2c5_pins_a: i2c5-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
+ <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c5_pins_sleep_a: i2c5-1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
+ <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */
+
+ };
+ };
+
+ i2s2_pins_a: i2s2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */
+ <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
+ <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ i2s2_pins_sleep_a: i2s2-1 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */
+ <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
+ <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
+ };
+ };
+
+ ltdc_pins_a: ltdc-a-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
+ <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
+ <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
+ <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
+ <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */
+ <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
+ <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
+ <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
+ <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
+ <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */
+ <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
+ <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
+ <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
+ <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */
+ <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
+ <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */
+ <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
+ <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */
+ <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
+ <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */
+ <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
+ <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
+ <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
+ <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
+ <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */
+ <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
+ <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
+ <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ ltdc_pins_sleep_a: ltdc-a-1 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
+ <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
+ <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
+ <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */
+ <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */
+ <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
+ <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
+ <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
+ <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
+ <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */
+ <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
+ <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
+ <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
+ <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */
+ <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
+ <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */
+ <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
+ <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */
+ <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */
+ <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */
+ <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
+ <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
+ <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
+ <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
+ <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */
+ <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
+ <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
+ <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */
+ };
+ };
+
+ ltdc_pins_b: ltdc-b-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
+ <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
+ <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
+ <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */
+ <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
+ <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
+ <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
+ <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
+ <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
+ <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
+ <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
+ <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
+ <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
+ <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
+ <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
+ <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
+ <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
+ <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
+ <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
+ <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
+ <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
+ <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
+ <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
+ <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */
+ <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
+ <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
+ <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
+ <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ ltdc_pins_sleep_b: ltdc-b-1 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
+ <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */
+ <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */
+ <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */
+ <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */
+ <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */
+ <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */
+ <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */
+ <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */
+ <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */
+ <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */
+ <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */
+ <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */
+ <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */
+ <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
+ <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */
+ <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */
+ <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */
+ <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */
+ <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */
+ <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */
+ <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */
+ <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */
+ <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */
+ <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */
+ <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */
+ <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */
+ <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */
+ };
+ };
+
+ m_can1_pins_a: m-can1-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
+ bias-disable;
+ };
+ };
+
+ m_can1_sleep_pins_a: m_can1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
+ <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
+ };
+ };
+
+ pwm1_pins_a: pwm1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */
+ <STM32_PINMUX('E', 11, AF1)>, /* TIM1_CH2 */
+ <STM32_PINMUX('E', 14, AF1)>; /* TIM1_CH4 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm1_sleep_pins_a: pwm1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */
+ <STM32_PINMUX('E', 11, ANALOG)>, /* TIM1_CH2 */
+ <STM32_PINMUX('E', 14, ANALOG)>; /* TIM1_CH4 */
+ };
+ };
+
+ pwm2_pins_a: pwm2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm2_sleep_pins_a: pwm2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */
+ };
+ };
+
+ pwm3_pins_a: pwm3-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 7, AF2)>; /* TIM3_CH2 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm3_sleep_pins_a: pwm3-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM3_CH2 */
+ };
+ };
+
+ pwm4_pins_a: pwm4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */
+ <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm4_sleep_pins_a: pwm4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */
+ <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */
+ };
+ };
+
+ pwm4_pins_b: pwm4-1 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm4_sleep_pins_b: pwm4-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
+ };
+ };
+
+ pwm5_pins_a: pwm5-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 11, AF2)>; /* TIM5_CH2 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm5_sleep_pins_a: pwm5-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 11, ANALOG)>; /* TIM5_CH2 */
+ };
+ };
+
+ pwm8_pins_a: pwm8-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm8_sleep_pins_a: pwm8-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 2, ANALOG)>; /* TIM8_CH4 */
+ };
+ };
+
+ pwm12_pins_a: pwm12-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm12_sleep_pins_a: pwm12-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 6, ANALOG)>; /* TIM12_CH1 */
+ };
+ };
+
+ qspi_clk_pins_a: qspi-clk-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ };
+
+ qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
+ };
+ };
+
+ qspi_bk1_pins_a: qspi-bk1-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
+ <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
+ <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
+ <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
+ <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
+ <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
+ };
+ };
+
+ qspi_bk2_pins_a: qspi-bk2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
+ <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
+ <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
+ <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
+ <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
+ <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
+ <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
+ <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
+ };
+ };
+
+ sai2a_pins_a: sai2a-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
+ <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
+ <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
+ <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
+ slew-rate = <0>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sai2a_sleep_pins_a: sai2a-1 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */
+ <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
+ <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
+ <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */
+ };
+ };
+
+ sai2b_pins_a: sai2b-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */
+ <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */
+ <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */
+ slew-rate = <0>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
+ bias-disable;
+ };
+ };
+
+ sai2b_sleep_pins_a: sai2b-1 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
+ <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */
+ <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */
+ <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */
+ };
+ };
+
+ sai2b_pins_b: sai2b-2 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
+ bias-disable;
+ };
+ };
+
+ sai2b_sleep_pins_b: sai2b-3 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
+ };
+ };
+
+ sai4a_pins_a: sai4a-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
+ slew-rate = <0>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sai4a_sleep_pins_a: sai4a-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */
+ };
+ };
+
+ sdmmc1_b4_pins_a: sdmmc1-b4-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ slew-rate = <1>;
+ drive-open-drain;
+ bias-disable;
+ };
+ };
+
+ sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
+ <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
+ };
+ };
+
+ sdmmc1_dir_pins_a: sdmmc1-dir-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
+ <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
+ <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2{
+ pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
+ bias-pull-up;
+ };
+ };
+
+ sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
+ <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
+ <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
+ <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
+ };
+ };
+
+ sdmmc2_b4_pins_a: sdmmc2-b4-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-open-drain;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
+ <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
+ };
+ };
+
+ sdmmc2_b4_pins_b: sdmmc2-b4-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-open-drain;
+ bias-disable;
+ };
+ };
+
+ sdmmc2_d47_pins_a: sdmmc2-d47-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
+ };
+ };
+
+ sdmmc3_b4_pins_a: sdmmc3-b4-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
+ <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-open-drain;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
+ <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
+ <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */
+ };
+ };
+
+ spdifrx_pins_a: spdifrx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
+ bias-disable;
+ };
+ };
+
+ spdifrx_sleep_pins_a: spdifrx-1 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
+ };
+ };
+
+ uart4_pins_a: uart4-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
+
+ uart4_pins_b: uart4-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
+
+ uart7_pins_a: uart7-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */
+ <STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */
+ <STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */
+ bias-disable;
+ };
+ };
+};
+
+&pinctrl_z {
+ i2c2_pins_b2: i2c2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c2_pins_sleep_b2: i2c2-1 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */
+ };
+ };
+
+ i2c4_pins_a: i2c4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
+ <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c4_pins_sleep_a: i2c4-1 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
+ <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
+ };
+ };
+
+ spi1_pins_a: spi1-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
+ <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
+ bias-disable;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi
index ed8b258256d7..fb41d0778b00 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -20,12 +20,6 @@
device_type = "cpu";
reg = <0>;
};
-
- cpu1: cpu@1 {
- compatible = "arm,cortex-a7";
- device_type = "cpu";
- reg = <1>;
- };
};
psci {
@@ -148,6 +142,11 @@
reg = <1>;
status = "disabled";
};
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
};
timers3: timer@40001000 {
@@ -177,6 +176,11 @@
reg = <2>;
status = "disabled";
};
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
};
timers4: timer@40002000 {
@@ -204,6 +208,11 @@
reg = <3>;
status = "disabled";
};
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
};
timers5: timer@40003000 {
@@ -233,6 +242,11 @@
reg = <4>;
status = "disabled";
};
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
};
timers6: timer@40004000 {
@@ -589,6 +603,11 @@
reg = <0>;
status = "disabled";
};
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
};
timers8: timer@44001000 {
@@ -620,6 +639,11 @@
reg = <7>;
status = "disabled";
};
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
};
usart6: serial@44003000 {
@@ -923,33 +947,7 @@
};
};
- m_can1: can@4400e000 {
- compatible = "bosch,m_can";
- reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
- reg-names = "m_can", "message_ram";
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
- clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
- status = "disabled";
- };
-
- m_can2: can@4400f000 {
- compatible = "bosch,m_can";
- reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
- reg-names = "m_can", "message_ram";
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
- clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
- status = "disabled";
- };
-
- dma1: dma@48000000 {
+ dma1: dma-controller@48000000 {
compatible = "st,stm32-dma";
reg = <0x48000000 0x400>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
@@ -966,7 +964,7 @@
dma-requests = <8>;
};
- dma2: dma@48001000 {
+ dma2: dma-controller@48001000 {
compatible = "st,stm32-dma";
reg = <0x48001000 0x400>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
@@ -1030,6 +1028,21 @@
};
};
+ sdmmc3: sdmmc@48004000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x10153180>;
+ reg = <0x48004000 0x400>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&rcc SDMMC3_K>;
+ clock-names = "apb_pclk";
+ resets = <&rcc SDMMC3_R>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <120000000>;
+ status = "disabled";
+ };
+
usbotg_hs: usb-otg@49000000 {
compatible = "snps,dwc2";
reg = <0x49000000 0x10000>;
@@ -1242,15 +1255,6 @@
status = "disabled";
};
- cryp1: cryp@54001000 {
- compatible = "st,stm32mp1-cryp";
- reg = <0x54001000 0x400>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc CRYP1>;
- resets = <&rcc CRYP1_R>;
- status = "disabled";
- };
-
hash1: hash@54002000 {
compatible = "st,stm32f756-hash";
reg = <0x54002000 0x400>;
@@ -1271,7 +1275,7 @@
status = "disabled";
};
- mdma1: dma@58000000 {
+ mdma1: dma-controller@58000000 {
compatible = "st,stm32h7-mdma";
reg = <0x58000000 0x1000>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
@@ -1318,13 +1322,29 @@
arm,primecell-periphid = <0x10153180>;
reg = <0x58005000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
+ interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC1_K>;
clock-names = "apb_pclk";
resets = <&rcc SDMMC1_R>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <120000000>;
+ status = "disabled";
+ };
+
+ sdmmc2: sdmmc@58007000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x10153180>;
+ reg = <0x58007000 0x1000>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&rcc SDMMC2_K>;
+ clock-names = "apb_pclk";
+ resets = <&rcc SDMMC2_R>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <120000000>;
+ status = "disabled";
};
crc1: crc@58009000 {
@@ -1349,16 +1369,15 @@
clock-names = "stmmaceth",
"mac-clk-tx",
"mac-clk-rx",
- "ethstp",
- "syscfg-clk";
+ "ethstp";
clocks = <&rcc ETHMAC>,
<&rcc ETHTX>,
<&rcc ETHRX>,
- <&rcc ETHSTP>,
- <&rcc SYSCFG>;
+ <&rcc ETHSTP>;
st,syscon = <&syscfg 0x4>;
snps,mixed-burst;
snps,pbl = <2>;
+ snps,en-tx-lpi-clockgating;
snps,axi-config = <&stmmac_axi_config_0>;
snps,tso;
status = "disabled";
@@ -1383,26 +1402,6 @@
status = "disabled";
};
- gpu: gpu@59000000 {
- compatible = "vivante,gc";
- reg = <0x59000000 0x800>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc GPU>, <&rcc GPU_K>;
- clock-names = "bus" ,"core";
- resets = <&rcc GPU_R>;
- status = "disabled";
- };
-
- dsi: dsi@5a000000 {
- compatible = "st,stm32-dsi";
- reg = <0x5a000000 0x800>;
- clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
- clock-names = "pclk", "ref", "px_clk";
- resets = <&rcc DSI_R>;
- reset-names = "apb";
- status = "disabled";
- };
-
ltdc: display-controller@5a001000 {
compatible = "st,stm32-ltdc";
reg = <0x5a001000 0x400>;
@@ -1486,7 +1485,7 @@
status = "disabled";
};
- bsec: nvmem@5c005000 {
+ bsec: efuse@5c005000 {
compatible = "st,stm32mp15-bsec";
reg = <0x5c005000 0x400>;
#address-cells = <1>;
@@ -1511,12 +1510,170 @@
#size-cells = <0>;
status = "disabled";
};
+
+ /*
+ * Break node order to solve dependency probe issue between
+ * pinctrl and exti.
+ */
+ pinctrl: pin-controller@50002000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp157-pinctrl";
+ ranges = <0 0x50002000 0xa400>;
+ interrupt-parent = <&exti>;
+ st,syscfg = <&exti 0x60 0xff>;
+ pins-are-numbered;
+
+ gpioa: gpio@50002000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x400>;
+ clocks = <&rcc GPIOA>;
+ st,bank-name = "GPIOA";
+ status = "disabled";
+ };
+
+ gpiob: gpio@50003000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1000 0x400>;
+ clocks = <&rcc GPIOB>;
+ st,bank-name = "GPIOB";
+ status = "disabled";
+ };
+
+ gpioc: gpio@50004000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x2000 0x400>;
+ clocks = <&rcc GPIOC>;
+ st,bank-name = "GPIOC";
+ status = "disabled";
+ };
+
+ gpiod: gpio@50005000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x3000 0x400>;
+ clocks = <&rcc GPIOD>;
+ st,bank-name = "GPIOD";
+ status = "disabled";
+ };
+
+ gpioe: gpio@50006000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x4000 0x400>;
+ clocks = <&rcc GPIOE>;
+ st,bank-name = "GPIOE";
+ status = "disabled";
+ };
+
+ gpiof: gpio@50007000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x5000 0x400>;
+ clocks = <&rcc GPIOF>;
+ st,bank-name = "GPIOF";
+ status = "disabled";
+ };
+
+ gpiog: gpio@50008000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x6000 0x400>;
+ clocks = <&rcc GPIOG>;
+ st,bank-name = "GPIOG";
+ status = "disabled";
+ };
+
+ gpioh: gpio@50009000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x7000 0x400>;
+ clocks = <&rcc GPIOH>;
+ st,bank-name = "GPIOH";
+ status = "disabled";
+ };
+
+ gpioi: gpio@5000a000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x8000 0x400>;
+ clocks = <&rcc GPIOI>;
+ st,bank-name = "GPIOI";
+ status = "disabled";
+ };
+
+ gpioj: gpio@5000b000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x9000 0x400>;
+ clocks = <&rcc GPIOJ>;
+ st,bank-name = "GPIOJ";
+ status = "disabled";
+ };
+
+ gpiok: gpio@5000c000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0xa000 0x400>;
+ clocks = <&rcc GPIOK>;
+ st,bank-name = "GPIOK";
+ status = "disabled";
+ };
+ };
+
+ pinctrl_z: pin-controller-z@54004000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp157-z-pinctrl";
+ ranges = <0 0x54004000 0x400>;
+ pins-are-numbered;
+ interrupt-parent = <&exti>;
+ st,syscfg = <&exti 0x60 0xff>;
+
+ gpioz: gpio@54004000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0 0x400>;
+ clocks = <&rcc GPIOZ>;
+ st,bank-name = "GPIOZ";
+ st,bank-ioport = <11>;
+ status = "disabled";
+ };
+ };
};
- mlahb {
- compatible = "simple-bus";
+ mlahb: ahb {
+ compatible = "st,mlahb", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
+ ranges;
dma-ranges = <0x00000000 0x38000000 0x10000>,
<0x10000000 0x10000000 0x60000>,
<0x30000000 0x30000000 0x60000>;
diff --git a/arch/arm/boot/dts/stm32mp153.dtsi b/arch/arm/boot/dts/stm32mp153.dtsi
new file mode 100644
index 000000000000..2d759fc6015c
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp153.dtsi
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+#include "stm32mp151.dtsi"
+
+/ {
+ cpus {
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ };
+ };
+
+ soc {
+ m_can1: can@4400e000 {
+ compatible = "bosch,m_can";
+ reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+ clock-names = "hclk", "cclk";
+ bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
+ status = "disabled";
+ };
+
+ m_can2: can@4400f000 {
+ compatible = "bosch,m_can";
+ reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+ clock-names = "hclk", "cclk";
+ bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
deleted file mode 100644
index 3d1ecb408b03..000000000000
--- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
+++ /dev/null
@@ -1,953 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
- */
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
-
-/ {
- soc {
- pinctrl: pin-controller@50002000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stm32mp157-pinctrl";
- ranges = <0 0x50002000 0xa400>;
- interrupt-parent = <&exti>;
- st,syscfg = <&exti 0x60 0xff>;
- pins-are-numbered;
-
- gpioa: gpio@50002000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x0 0x400>;
- clocks = <&rcc GPIOA>;
- st,bank-name = "GPIOA";
- status = "disabled";
- };
-
- gpiob: gpio@50003000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x400>;
- clocks = <&rcc GPIOB>;
- st,bank-name = "GPIOB";
- status = "disabled";
- };
-
- gpioc: gpio@50004000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x400>;
- clocks = <&rcc GPIOC>;
- st,bank-name = "GPIOC";
- status = "disabled";
- };
-
- gpiod: gpio@50005000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x3000 0x400>;
- clocks = <&rcc GPIOD>;
- st,bank-name = "GPIOD";
- status = "disabled";
- };
-
- gpioe: gpio@50006000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x4000 0x400>;
- clocks = <&rcc GPIOE>;
- st,bank-name = "GPIOE";
- status = "disabled";
- };
-
- gpiof: gpio@50007000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x5000 0x400>;
- clocks = <&rcc GPIOF>;
- st,bank-name = "GPIOF";
- status = "disabled";
- };
-
- gpiog: gpio@50008000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x6000 0x400>;
- clocks = <&rcc GPIOG>;
- st,bank-name = "GPIOG";
- status = "disabled";
- };
-
- gpioh: gpio@50009000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x7000 0x400>;
- clocks = <&rcc GPIOH>;
- st,bank-name = "GPIOH";
- status = "disabled";
- };
-
- gpioi: gpio@5000a000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x8000 0x400>;
- clocks = <&rcc GPIOI>;
- st,bank-name = "GPIOI";
- status = "disabled";
- };
-
- gpioj: gpio@5000b000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x9000 0x400>;
- clocks = <&rcc GPIOJ>;
- st,bank-name = "GPIOJ";
- status = "disabled";
- };
-
- gpiok: gpio@5000c000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0xa000 0x400>;
- clocks = <&rcc GPIOK>;
- st,bank-name = "GPIOK";
- status = "disabled";
- };
-
- adc12_ain_pins_a: adc12-ain-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */
- <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
- <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */
- <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */
- };
- };
-
- adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
- <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
- };
- };
-
- cec_pins_a: cec-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 15, AF4)>;
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- cec_pins_sleep_a: cec-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
- };
- };
-
- cec_pins_b: cec-1 {
- pins {
- pinmux = <STM32_PINMUX('B', 6, AF5)>;
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- cec_pins_sleep_b: cec-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
- };
- };
-
- dac_ch1_pins_a: dac-ch1 {
- pins {
- pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
- };
- };
-
- dac_ch2_pins_a: dac-ch2 {
- pins {
- pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
- };
- };
-
- dcmi_pins_a: dcmi-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
- <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
- <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
- <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
- <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
- <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
- <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */
- <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
- <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
- <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
- <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
- <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
- <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */
- <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */
- <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
- bias-disable;
- };
- };
-
- dcmi_sleep_pins_a: dcmi-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
- <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
- <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
- <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
- <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
- <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
- <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */
- <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
- <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
- <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
- <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
- <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
- <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */
- <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */
- <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */
- };
- };
-
- ethernet0_rgmii_pins_a: rgmii-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
- <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
- <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
- bias-disable;
- drive-push-pull;
- slew-rate = <3>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
- <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
- bias-disable;
- };
- };
-
- ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
- <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
- <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
- <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
- <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
- };
- };
-
- fmc_pins_a: fmc-0 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
- <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
- <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
- <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
- <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
- <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
- <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
- <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
- <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
- <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
- <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
- <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
- <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
- bias-pull-up;
- };
- };
-
- fmc_sleep_pins_a: fmc-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
- <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
- <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */
- <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */
- <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
- <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
- <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
- <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
- <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
- <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
- <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
- <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
- <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */
- <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
- };
- };
-
- i2c1_pins_a: i2c1-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
- <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c1_pins_sleep_a: i2c1-1 {
- pins {
- pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
- <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
- };
- };
-
- i2c1_pins_b: i2c1-2 {
- pins {
- pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
- <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c1_pins_sleep_b: i2c1-3 {
- pins {
- pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */
- <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
- };
- };
-
- i2c2_pins_a: i2c2-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
- <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c2_pins_sleep_a: i2c2-1 {
- pins {
- pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
- <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
- };
- };
-
- i2c2_pins_b1: i2c2-2 {
- pins {
- pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c2_pins_sleep_b1: i2c2-3 {
- pins {
- pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
- };
- };
-
- i2c5_pins_a: i2c5-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
- <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c5_pins_sleep_a: i2c5-1 {
- pins {
- pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
- <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */
-
- };
- };
-
- i2s2_pins_a: i2s2-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */
- <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
- <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- i2s2_pins_sleep_a: i2s2-1 {
- pins {
- pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */
- <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
- <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
- };
- };
-
- ltdc_pins_a: ltdc-a-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
- <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
- <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
- <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
- <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */
- <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
- <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
- <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
- <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
- <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */
- <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
- <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
- <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
- <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */
- <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
- <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */
- <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
- <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */
- <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
- <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */
- <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
- <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
- <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
- <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
- <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */
- <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
- <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
- <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- ltdc_pins_sleep_a: ltdc-a-1 {
- pins {
- pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
- <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
- <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
- <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */
- <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */
- <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
- <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
- <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
- <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
- <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */
- <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
- <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
- <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
- <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */
- <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
- <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */
- <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
- <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */
- <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */
- <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */
- <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
- <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
- <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
- <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
- <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */
- <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
- <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
- <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */
- };
- };
-
- ltdc_pins_b: ltdc-b-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
- <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
- <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
- <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */
- <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
- <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
- <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
- <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
- <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
- <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
- <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
- <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
- <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
- <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
- <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
- <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
- <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
- <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
- <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
- <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
- <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
- <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
- <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
- <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */
- <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
- <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
- <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
- <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- ltdc_pins_sleep_b: ltdc-b-1 {
- pins {
- pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
- <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */
- <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */
- <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */
- <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */
- <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */
- <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */
- <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */
- <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */
- <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */
- <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */
- <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */
- <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */
- <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */
- <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
- <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */
- <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */
- <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */
- <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */
- <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */
- <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */
- <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */
- <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */
- <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */
- <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */
- <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */
- <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */
- <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */
- };
- };
-
- m_can1_pins_a: m-can1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
- bias-disable;
- };
- };
-
- m_can1_sleep_pins_a: m_can1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
- <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
- };
- };
-
- pwm2_pins_a: pwm2-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm8_pins_a: pwm8-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm12_pins_a: pwm12-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- qspi_clk_pins_a: qspi-clk-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
- bias-disable;
- drive-push-pull;
- slew-rate = <3>;
- };
- };
-
- qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
- };
- };
-
- qspi_bk1_pins_a: qspi-bk1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
- <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
- <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
- <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
- bias-pull-up;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
- <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
- <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
- <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
- <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
- };
- };
-
- qspi_bk2_pins_a: qspi-bk2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
- <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
- <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
- <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
- bias-pull-up;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
- <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
- <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
- <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
- <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
- };
- };
-
- sai2a_pins_a: sai2a-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
- <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
- <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
- <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
- slew-rate = <0>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sai2a_sleep_pins_a: sai2a-1 {
- pins {
- pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */
- <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
- <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
- <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */
- };
- };
-
- sai2b_pins_a: sai2b-0 {
- pins1 {
- pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */
- <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */
- <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */
- slew-rate = <0>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
- bias-disable;
- };
- };
-
- sai2b_sleep_pins_a: sai2b-1 {
- pins {
- pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
- <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */
- <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */
- <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */
- };
- };
-
- sai2b_pins_b: sai2b-2 {
- pins {
- pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
- bias-disable;
- };
- };
-
- sai2b_sleep_pins_b: sai2b-3 {
- pins {
- pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
- };
- };
-
- sai4a_pins_a: sai4a-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
- slew-rate = <0>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sai4a_sleep_pins_a: sai4a-1 {
- pins {
- pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */
- };
- };
-
- sdmmc1_b4_pins_a: sdmmc1-b4-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
- <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <3>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
- slew-rate = <3>;
- drive-push-pull;
- bias-disable;
- };
- pins2{
- pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <3>;
- drive-open-drain;
- bias-disable;
- };
- };
-
- sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
- <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
- };
- };
-
- sdmmc1_dir_pins_a: sdmmc1-dir-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
- <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
- <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
- slew-rate = <3>;
- drive-push-pull;
- bias-pull-up;
- };
- pins2{
- pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
- bias-pull-up;
- };
- };
-
- sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
- <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
- <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
- <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
- };
- };
-
- spdifrx_pins_a: spdifrx-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
- bias-disable;
- };
- };
-
- spdifrx_sleep_pins_a: spdifrx-1 {
- pins {
- pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
- };
- };
-
- uart4_pins_a: uart4-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart4_pins_b: uart4-1 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart7_pins_a: uart7-0 {
- pins1 {
- pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */
- <STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */
- <STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */
- bias-disable;
- };
- };
- };
-
- pinctrl_z: pin-controller-z@54004000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stm32mp157-z-pinctrl";
- ranges = <0 0x54004000 0x400>;
- pins-are-numbered;
- interrupt-parent = <&exti>;
- st,syscfg = <&exti 0x60 0xff>;
-
- gpioz: gpio@54004000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0 0x400>;
- clocks = <&rcc GPIOZ>;
- st,bank-name = "GPIOZ";
- st,bank-ioport = <11>;
- status = "disabled";
- };
-
- i2c2_pins_b2: i2c2-0 {
- pins {
- pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c2_pins_sleep_b2: i2c2-1 {
- pins {
- pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */
- };
- };
-
- i2c4_pins_a: i2c4-0 {
- pins {
- pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
- <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c4_pins_sleep_a: i2c4-1 {
- pins {
- pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
- <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
- };
- };
-
- spi1_pins_a: spi1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
- <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
- bias-disable;
- };
- };
- };
- };
-};
diff --git a/arch/arm/boot/dts/stm32mp157.dtsi b/arch/arm/boot/dts/stm32mp157.dtsi
new file mode 100644
index 000000000000..3f0a4a91cce6
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+#include "stm32mp153.dtsi"
+
+/ {
+ soc {
+ gpu: gpu@59000000 {
+ compatible = "vivante,gc";
+ reg = <0x59000000 0x800>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc GPU>, <&rcc GPU_K>;
+ clock-names = "bus" ,"core";
+ resets = <&rcc GPU_R>;
+ status = "disabled";
+ };
+
+ dsi: dsi@5a000000 {
+ compatible = "st,stm32-dsi";
+ reg = <0x5a000000 0x800>;
+ clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
+ clock-names = "pclk", "ref", "px_clk";
+ resets = <&rcc DSI_R>;
+ reset-names = "apb";
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts
index 628c74a45a25..cbfa4075907e 100644
--- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts
+++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts
@@ -6,8 +6,9 @@
/dts-v1/;
-#include "stm32mp157c.dtsi"
-#include "stm32mp157xac-pinctrl.dtsi"
+#include "stm32mp157.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxac-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mfd/st,stpmic1.h>
diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts b/arch/arm/boot/dts/stm32mp157a-dk1.dts
index 984a47cbd13d..d03d4cd2606a 100644
--- a/arch/arm/boot/dts/stm32mp157a-dk1.dts
+++ b/arch/arm/boot/dts/stm32mp157a-dk1.dts
@@ -6,10 +6,10 @@
/dts-v1/;
-#include "stm32mp157c.dtsi"
-#include "stm32mp157xac-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/mfd/st,stpmic1.h>
+#include "stm32mp157.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxac-pinctrl.dtsi"
+#include "stm32mp15xx-dkx.dtsi"
/ {
model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
@@ -23,494 +23,4 @@
chosen {
stdout-path = "serial0:115200n8";
};
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xc0000000 0x20000000>;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- mcuram2: mcuram2@10000000 {
- compatible = "shared-dma-pool";
- reg = <0x10000000 0x40000>;
- no-map;
- };
-
- vdev0vring0: vdev0vring0@10040000 {
- compatible = "shared-dma-pool";
- reg = <0x10040000 0x1000>;
- no-map;
- };
-
- vdev0vring1: vdev0vring1@10041000 {
- compatible = "shared-dma-pool";
- reg = <0x10041000 0x1000>;
- no-map;
- };
-
- vdev0buffer: vdev0buffer@10042000 {
- compatible = "shared-dma-pool";
- reg = <0x10042000 0x4000>;
- no-map;
- };
-
- mcuram: mcuram@30000000 {
- compatible = "shared-dma-pool";
- reg = <0x30000000 0x40000>;
- no-map;
- };
-
- retram: retram@38000000 {
- compatible = "shared-dma-pool";
- reg = <0x38000000 0x10000>;
- no-map;
- };
-
- gpu_reserved: gpu@d4000000 {
- reg = <0xd4000000 0x4000000>;
- no-map;
- };
- };
-
- led {
- compatible = "gpio-leds";
- blue {
- label = "heartbeat";
- gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
- };
-
- sound {
- compatible = "audio-graph-card";
- label = "STM32MP1-DK";
- routing =
- "Playback" , "MCLK",
- "Capture" , "MCLK",
- "MICL" , "Mic Bias";
- dais = <&sai2a_port &sai2b_port &i2s2_port>;
- status = "okay";
- };
-};
-
-&adc {
- pinctrl-names = "default";
- pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>;
- vdd-supply = <&vdd>;
- vdda-supply = <&vdd>;
- vref-supply = <&vrefbuf>;
- status = "disabled";
- adc1: adc@0 {
- /*
- * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
- * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
- * 5 * (56 + 47kOhms) * 5pF => 2.5us.
- * Use arbitrary margin here (e.g. 5us).
- */
- st,min-sample-time-nsecs = <5000>;
- /* AIN connector, USB Type-C CC1 & CC2 */
- st,adc-channels = <0 1 6 13 18 19>;
- status = "okay";
- };
- adc2: adc@100 {
- /* AIN connector, USB Type-C CC1 & CC2 */
- st,adc-channels = <0 1 2 6 18 19>;
- st,min-sample-time-nsecs = <5000>;
- status = "okay";
- };
-};
-
-&cec {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&cec_pins_b>;
- pinctrl-1 = <&cec_pins_sleep_b>;
- status = "okay";
-};
-
-&ethernet0 {
- status = "okay";
- pinctrl-0 = <&ethernet0_rgmii_pins_a>;
- pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
- pinctrl-names = "default", "sleep";
- phy-mode = "rgmii-id";
- max-speed = <1000>;
- phy-handle = <&phy0>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-};
-
-&gpu {
- contiguous-area = <&gpu_reserved>;
- status = "okay";
-};
-
-&i2c1 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c1_pins_a>;
- pinctrl-1 = <&i2c1_pins_sleep_a>;
- i2c-scl-rising-time-ns = <100>;
- i2c-scl-falling-time-ns = <7>;
- status = "okay";
- /delete-property/dmas;
- /delete-property/dma-names;
-
- hdmi-transmitter@39 {
- compatible = "sil,sii9022";
- reg = <0x39>;
- iovcc-supply = <&v3v3_hdmi>;
- cvcc12-supply = <&v1v2_hdmi>;
- reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>;
- interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
- interrupt-parent = <&gpiog>;
- #sound-dai-cells = <0>;
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- sii9022_in: endpoint {
- remote-endpoint = <&ltdc_ep0_out>;
- };
- };
-
- port@3 {
- reg = <3>;
- sii9022_tx_endpoint: endpoint {
- remote-endpoint = <&i2s2_endpoint>;
- };
- };
- };
- };
-
- cs42l51: cs42l51@4a {
- compatible = "cirrus,cs42l51";
- reg = <0x4a>;
- #sound-dai-cells = <0>;
- VL-supply = <&v3v3>;
- VD-supply = <&v1v8_audio>;
- VA-supply = <&v1v8_audio>;
- VAHP-supply = <&v1v8_audio>;
- reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
- clocks = <&sai2a>;
- clock-names = "MCLK";
- status = "okay";
-
- cs42l51_port: port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cs42l51_tx_endpoint: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&sai2a_endpoint>;
- frame-master;
- bitclock-master;
- };
-
- cs42l51_rx_endpoint: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&sai2b_endpoint>;
- frame-master;
- bitclock-master;
- };
- };
- };
-};
-
-&i2c4 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
-
- pmic: stpmic@33 {
- compatible = "st,stpmic1";
- reg = <0x33>;
- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <2>;
- status = "okay";
-
- regulators {
- compatible = "st,stpmic1-regulators";
- ldo1-supply = <&v3v3>;
- ldo3-supply = <&vdd_ddr>;
- ldo6-supply = <&v3v3>;
- pwr_sw1-supply = <&bst_out>;
- pwr_sw2-supply = <&bst_out>;
-
- vddcore: buck1 {
- regulator-name = "vddcore";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- vdd_ddr: buck2 {
- regulator-name = "vdd_ddr";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- vdd: buck3 {
- regulator-name = "vdd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- st,mask-reset;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- v3v3: buck4 {
- regulator-name = "v3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-over-current-protection;
- regulator-initial-mode = <0>;
- };
-
- v1v8_audio: ldo1 {
- regulator-name = "v1v8_audio";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- interrupts = <IT_CURLIM_LDO1 0>;
- };
-
- v3v3_hdmi: ldo2 {
- regulator-name = "v3v3_hdmi";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- interrupts = <IT_CURLIM_LDO2 0>;
- };
-
- vtt_ddr: ldo3 {
- regulator-name = "vtt_ddr";
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <750000>;
- regulator-always-on;
- regulator-over-current-protection;
- };
-
- vdd_usb: ldo4 {
- regulator-name = "vdd_usb";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- interrupts = <IT_CURLIM_LDO4 0>;
- };
-
- vdda: ldo5 {
- regulator-name = "vdda";
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <2900000>;
- interrupts = <IT_CURLIM_LDO5 0>;
- regulator-boot-on;
- };
-
- v1v2_hdmi: ldo6 {
- regulator-name = "v1v2_hdmi";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- interrupts = <IT_CURLIM_LDO6 0>;
- };
-
- vref_ddr: vref_ddr {
- regulator-name = "vref_ddr";
- regulator-always-on;
- regulator-over-current-protection;
- };
-
- bst_out: boost {
- regulator-name = "bst_out";
- interrupts = <IT_OCP_BOOST 0>;
- };
-
- vbus_otg: pwr_sw1 {
- regulator-name = "vbus_otg";
- interrupts = <IT_OCP_OTG 0>;
- };
-
- vbus_sw: pwr_sw2 {
- regulator-name = "vbus_sw";
- interrupts = <IT_OCP_SWOUT 0>;
- regulator-active-discharge = <1>;
- };
- };
-
- onkey {
- compatible = "st,stpmic1-onkey";
- interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
- interrupt-names = "onkey-falling", "onkey-rising";
- power-off-time-sec = <10>;
- status = "okay";
- };
-
- watchdog {
- compatible = "st,stpmic1-wdt";
- status = "disabled";
- };
- };
-};
-
-&i2s2 {
- clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
- clock-names = "pclk", "i2sclk", "x8k", "x11k";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2s2_pins_a>;
- pinctrl-1 = <&i2s2_pins_sleep_a>;
- status = "okay";
-
- i2s2_port: port {
- i2s2_endpoint: endpoint {
- remote-endpoint = <&sii9022_tx_endpoint>;
- format = "i2s";
- mclk-fs = <256>;
- };
- };
-};
-
-&ipcc {
- status = "okay";
-};
-
-&iwdg2 {
- timeout-sec = <32>;
- status = "okay";
-};
-
-&ltdc {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&ltdc_pins_a>;
- pinctrl-1 = <&ltdc_pins_sleep_a>;
- status = "okay";
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ltdc_ep0_out: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&sii9022_in>;
- };
- };
-};
-
-&m4_rproc {
- memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
- <&vdev0vring1>, <&vdev0buffer>;
- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
- mbox-names = "vq0", "vq1", "shutdown";
- interrupt-parent = <&exti>;
- interrupts = <68 1>;
- status = "okay";
-};
-
-&pwr_regulators {
- vdd-supply = <&vdd>;
- vdd_3v3_usbfs-supply = <&vdd_usb>;
-};
-
-&rng1 {
- status = "okay";
-};
-
-&rtc {
- status = "okay";
-};
-
-&sai2 {
- clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
- clock-names = "pclk", "x8k", "x11k";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_b>;
- pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_b>;
- status = "okay";
-
- sai2a: audio-controller@4400b004 {
- #clock-cells = <0>;
- dma-names = "tx";
- clocks = <&rcc SAI2_K>;
- clock-names = "sai_ck";
- status = "okay";
-
- sai2a_port: port {
- sai2a_endpoint: endpoint {
- remote-endpoint = <&cs42l51_tx_endpoint>;
- format = "i2s";
- mclk-fs = <256>;
- dai-tdm-slot-num = <2>;
- dai-tdm-slot-width = <32>;
- };
- };
- };
-
- sai2b: audio-controller@4400b024 {
- dma-names = "rx";
- st,sync = <&sai2a 2>;
- clocks = <&rcc SAI2_K>, <&sai2a>;
- clock-names = "sai_ck", "MCLK";
- status = "okay";
-
- sai2b_port: port {
- sai2b_endpoint: endpoint {
- remote-endpoint = <&cs42l51_rx_endpoint>;
- format = "i2s";
- mclk-fs = <256>;
- dai-tdm-slot-num = <2>;
- dai-tdm-slot-width = <32>;
- };
- };
- };
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- broken-cd;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&v3v3>;
- status = "okay";
-};
-
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart4_pins_a>;
- status = "okay";
-};
-
-&vrefbuf {
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <2500000>;
- vdda-supply = <&vdd>;
- status = "okay";
};
diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts b/arch/arm/boot/dts/stm32mp157c-dk2.dts
index d26adcbeba33..7985b80967ca 100644
--- a/arch/arm/boot/dts/stm32mp157c-dk2.dts
+++ b/arch/arm/boot/dts/stm32mp157c-dk2.dts
@@ -6,11 +6,24 @@
/dts-v1/;
-#include "stm32mp157a-dk1.dts"
+#include "stm32mp157.dtsi"
+#include "stm32mp15xc.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxac-pinctrl.dtsi"
+#include "stm32mp15xx-dkx.dtsi"
/ {
model = "STMicroelectronics STM32MP157C-DK2 Discovery Board";
compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
+
+ aliases {
+ ethernet0 = &ethernet0;
+ serial0 = &uart4;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
};
&dsi {
diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts
index b8cc0fb0ec48..1fc43251d697 100644
--- a/arch/arm/boot/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts
@@ -5,8 +5,10 @@
*/
/dts-v1/;
-#include "stm32mp157c.dtsi"
-#include "stm32mp157xaa-pinctrl.dtsi"
+#include "stm32mp157.dtsi"
+#include "stm32mp15xc.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxaa-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mfd/st,stpmic1.h>
@@ -89,6 +91,22 @@
};
};
+&adc {
+ /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */
+ pinctrl-0 = <&adc1_in6_pins_a>;
+ pinctrl-names = "default";
+ vdd-supply = <&vdd>;
+ vdda-supply = <&vdda>;
+ vref-supply = <&vdda>;
+ status = "disabled";
+ adc1: adc@0 {
+ st,adc-channels = <0 1 6>;
+ /* 16.5 ck_cycles sampling time */
+ st,min-sample-time-nsecs = <400>;
+ status = "okay";
+ };
+};
+
&dac {
pinctrl-names = "default";
pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
@@ -305,6 +323,22 @@
status = "okay";
};
+&sdmmc2 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ st,neg-edge;
+ bus-width = <8>;
+ vmmc-supply = <&v3v3>;
+ vqmmc-supply = <&v3v3>;
+ mmc-ddr-3_3v;
+ status = "okay";
+};
+
&timers6 {
status = "okay";
/* spare dmas for other usage */
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts
index 3789312c8539..228e35e16884 100644
--- a/arch/arm/boot/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts
@@ -283,6 +283,18 @@
};
};
+&sdmmc3 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc3_b4_pins_a>;
+ pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
+ broken-cd;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&v3v3>;
+ status = "disabled";
+};
+
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins_a>;
@@ -296,7 +308,8 @@
status = "disabled";
pwm {
pinctrl-0 = <&pwm2_pins_a>;
- pinctrl-names = "default";
+ pinctrl-1 = <&pwm2_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
status = "okay";
};
timer@1 {
@@ -310,7 +323,8 @@
status = "disabled";
pwm {
pinctrl-0 = <&pwm8_pins_a>;
- pinctrl-names = "default";
+ pinctrl-1 = <&pwm8_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
status = "okay";
};
timer@7 {
@@ -324,7 +338,8 @@
status = "disabled";
pwm {
pinctrl-0 = <&pwm12_pins_a>;
- pinctrl-names = "default";
+ pinctrl-1 = <&pwm12_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
status = "okay";
};
timer@11 {
@@ -340,6 +355,7 @@
&usbotg_hs {
dr_mode = "peripheral";
phys = <&usbphyc_port1 0>;
+ phy-names = "usb2-phy";
status = "okay";
};
diff --git a/arch/arm/boot/dts/stm32mp157xaa-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157xaa-pinctrl.dtsi
deleted file mode 100644
index 875adf5e1e30..000000000000
--- a/arch/arm/boot/dts/stm32mp157xaa-pinctrl.dtsi
+++ /dev/null
@@ -1,90 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com>
- */
-
-#include "stm32mp157-pinctrl.dtsi"
-/ {
- soc {
- pinctrl: pin-controller@50002000 {
- st,package = <STM32MP_PKG_AA>;
-
- gpioa: gpio@50002000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@50003000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@50004000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@50005000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@50006000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@50007000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@50008000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@50009000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 112 16>;
- };
-
- gpioi: gpio@5000a000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 128 16>;
- };
-
- gpioj: gpio@5000b000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 144 16>;
- };
-
- gpiok: gpio@5000c000 {
- status = "okay";
- ngpios = <8>;
- gpio-ranges = <&pinctrl 0 160 8>;
- };
- };
-
- pinctrl_z: pin-controller-z@54004000 {
- st,package = <STM32MP_PKG_AA>;
-
- gpioz: gpio@54004000 {
- status = "okay";
- ngpios = <8>;
- gpio-ranges = <&pinctrl_z 0 400 8>;
- };
- };
- };
-};
diff --git a/arch/arm/boot/dts/stm32mp157xab-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157xab-pinctrl.dtsi
deleted file mode 100644
index 961fa12a59c3..000000000000
--- a/arch/arm/boot/dts/stm32mp157xab-pinctrl.dtsi
+++ /dev/null
@@ -1,62 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com>
- */
-
-#include "stm32mp157-pinctrl.dtsi"
-/ {
- soc {
- pinctrl: pin-controller@50002000 {
- st,package = <STM32MP_PKG_AB>;
-
- gpioa: gpio@50002000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@50003000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@50004000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@50005000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@50006000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@50007000 {
- status = "okay";
- ngpios = <6>;
- gpio-ranges = <&pinctrl 6 86 6>;
- };
-
- gpiog: gpio@50008000 {
- status = "okay";
- ngpios = <10>;
- gpio-ranges = <&pinctrl 6 102 10>;
- };
-
- gpioh: gpio@50009000 {
- status = "okay";
- ngpios = <2>;
- gpio-ranges = <&pinctrl 0 112 2>;
- };
- };
- };
-};
diff --git a/arch/arm/boot/dts/stm32mp157xac-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157xac-pinctrl.dtsi
deleted file mode 100644
index 26600f188d25..000000000000
--- a/arch/arm/boot/dts/stm32mp157xac-pinctrl.dtsi
+++ /dev/null
@@ -1,78 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com>
- */
-
-#include "stm32mp157-pinctrl.dtsi"
-/ {
- soc {
- pinctrl: pin-controller@50002000 {
- st,package = <STM32MP_PKG_AC>;
-
- gpioa: gpio@50002000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@50003000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@50004000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@50005000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@50006000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@50007000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@50008000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@50009000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 112 16>;
- };
-
- gpioi: gpio@5000a000 {
- status = "okay";
- ngpios = <12>;
- gpio-ranges = <&pinctrl 0 128 12>;
- };
- };
-
- pinctrl_z: pin-controller-z@54004000 {
- st,package = <STM32MP_PKG_AC>;
-
- gpioz: gpio@54004000 {
- status = "okay";
- ngpios = <8>;
- gpio-ranges = <&pinctrl_z 0 400 8>;
- };
- };
- };
-};
diff --git a/arch/arm/boot/dts/stm32mp157xad-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157xad-pinctrl.dtsi
deleted file mode 100644
index 910113f3e69a..000000000000
--- a/arch/arm/boot/dts/stm32mp157xad-pinctrl.dtsi
+++ /dev/null
@@ -1,62 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com>
- */
-
-#include "stm32mp157-pinctrl.dtsi"
-/ {
- soc {
- pinctrl: pin-controller@50002000 {
- st,package = <STM32MP_PKG_AD>;
-
- gpioa: gpio@50002000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@50003000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@50004000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@50005000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@50006000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@50007000 {
- status = "okay";
- ngpios = <6>;
- gpio-ranges = <&pinctrl 6 86 6>;
- };
-
- gpiog: gpio@50008000 {
- status = "okay";
- ngpios = <10>;
- gpio-ranges = <&pinctrl 6 102 10>;
- };
-
- gpioh: gpio@50009000 {
- status = "okay";
- ngpios = <2>;
- gpio-ranges = <&pinctrl 0 112 2>;
- };
- };
- };
-};
diff --git a/arch/arm/boot/dts/stm32mp15xc.dtsi b/arch/arm/boot/dts/stm32mp15xc.dtsi
new file mode 100644
index 000000000000..b06a55a2fa18
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xc.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+/ {
+ soc {
+ cryp1: cryp@54001000 {
+ compatible = "st,stm32mp1-cryp";
+ reg = <0x54001000 0x400>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CRYP1>;
+ resets = <&rcc CRYP1_R>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
new file mode 100644
index 000000000000..f6672e87aef3
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
@@ -0,0 +1,625 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mfd/st,stpmic1.h>
+
+/ {
+ memory@c0000000 {
+ device_type = "memory";
+ reg = <0xc0000000 0x20000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mcuram2: mcuram2@10000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10000000 0x40000>;
+ no-map;
+ };
+
+ vdev0vring0: vdev0vring0@10040000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10040000 0x1000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@10041000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10041000 0x1000>;
+ no-map;
+ };
+
+ vdev0buffer: vdev0buffer@10042000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10042000 0x4000>;
+ no-map;
+ };
+
+ mcuram: mcuram@30000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x30000000 0x40000>;
+ no-map;
+ };
+
+ retram: retram@38000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x38000000 0x10000>;
+ no-map;
+ };
+
+ gpu_reserved: gpu@d4000000 {
+ reg = <0xd4000000 0x4000000>;
+ no-map;
+ };
+ };
+
+ led {
+ compatible = "gpio-leds";
+ blue {
+ label = "heartbeat";
+ gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+ };
+
+ sound {
+ compatible = "audio-graph-card";
+ label = "STM32MP1-DK";
+ routing =
+ "Playback" , "MCLK",
+ "Capture" , "MCLK",
+ "MICL" , "Mic Bias";
+ dais = <&sai2a_port &sai2b_port &i2s2_port>;
+ status = "okay";
+ };
+};
+
+&adc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>;
+ vdd-supply = <&vdd>;
+ vdda-supply = <&vdd>;
+ vref-supply = <&vrefbuf>;
+ status = "disabled";
+ adc1: adc@0 {
+ /*
+ * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
+ * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
+ * 5 * (56 + 47kOhms) * 5pF => 2.5us.
+ * Use arbitrary margin here (e.g. 5us).
+ */
+ st,min-sample-time-nsecs = <5000>;
+ /* AIN connector, USB Type-C CC1 & CC2 */
+ st,adc-channels = <0 1 6 13 18 19>;
+ status = "okay";
+ };
+ adc2: adc@100 {
+ /* AIN connector, USB Type-C CC1 & CC2 */
+ st,adc-channels = <0 1 2 6 18 19>;
+ st,min-sample-time-nsecs = <5000>;
+ status = "okay";
+ };
+};
+
+&cec {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cec_pins_b>;
+ pinctrl-1 = <&cec_pins_sleep_b>;
+ status = "okay";
+};
+
+&ethernet0 {
+ status = "okay";
+ pinctrl-0 = <&ethernet0_rgmii_pins_a>;
+ pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rgmii-id";
+ max-speed = <1000>;
+ phy-handle = <&phy0>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&gpu {
+ contiguous-area = <&gpu_reserved>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c1_pins_a>;
+ pinctrl-1 = <&i2c1_pins_sleep_a>;
+ i2c-scl-rising-time-ns = <100>;
+ i2c-scl-falling-time-ns = <7>;
+ status = "okay";
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ hdmi-transmitter@39 {
+ compatible = "sil,sii9022";
+ reg = <0x39>;
+ iovcc-supply = <&v3v3_hdmi>;
+ cvcc12-supply = <&v1v2_hdmi>;
+ reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&gpiog>;
+ #sound-dai-cells = <0>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ sii9022_in: endpoint {
+ remote-endpoint = <&ltdc_ep0_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ sii9022_tx_endpoint: endpoint {
+ remote-endpoint = <&i2s2_endpoint>;
+ };
+ };
+ };
+ };
+
+ cs42l51: cs42l51@4a {
+ compatible = "cirrus,cs42l51";
+ reg = <0x4a>;
+ #sound-dai-cells = <0>;
+ VL-supply = <&v3v3>;
+ VD-supply = <&v1v8_audio>;
+ VA-supply = <&v1v8_audio>;
+ VAHP-supply = <&v1v8_audio>;
+ reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
+ clocks = <&sai2a>;
+ clock-names = "MCLK";
+ status = "okay";
+
+ cs42l51_port: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cs42l51_tx_endpoint: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&sai2a_endpoint>;
+ frame-master;
+ bitclock-master;
+ };
+
+ cs42l51_rx_endpoint: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&sai2b_endpoint>;
+ frame-master;
+ bitclock-master;
+ };
+ };
+ };
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ pmic: stpmic@33 {
+ compatible = "st,stpmic1";
+ reg = <0x33>;
+ interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "okay";
+
+ regulators {
+ compatible = "st,stpmic1-regulators";
+ ldo1-supply = <&v3v3>;
+ ldo3-supply = <&vdd_ddr>;
+ ldo6-supply = <&v3v3>;
+ pwr_sw1-supply = <&bst_out>;
+ pwr_sw2-supply = <&bst_out>;
+
+ vddcore: buck1 {
+ regulator-name = "vddcore";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd_ddr: buck2 {
+ regulator-name = "vdd_ddr";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd: buck3 {
+ regulator-name = "vdd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ st,mask-reset;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ v3v3: buck4 {
+ regulator-name = "v3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-over-current-protection;
+ regulator-initial-mode = <0>;
+ };
+
+ v1v8_audio: ldo1 {
+ regulator-name = "v1v8_audio";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ interrupts = <IT_CURLIM_LDO1 0>;
+ };
+
+ v3v3_hdmi: ldo2 {
+ regulator-name = "v3v3_hdmi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ interrupts = <IT_CURLIM_LDO2 0>;
+ };
+
+ vtt_ddr: ldo3 {
+ regulator-name = "vtt_ddr";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <750000>;
+ regulator-always-on;
+ regulator-over-current-protection;
+ };
+
+ vdd_usb: ldo4 {
+ regulator-name = "vdd_usb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ interrupts = <IT_CURLIM_LDO4 0>;
+ };
+
+ vdda: ldo5 {
+ regulator-name = "vdda";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ interrupts = <IT_CURLIM_LDO5 0>;
+ regulator-boot-on;
+ };
+
+ v1v2_hdmi: ldo6 {
+ regulator-name = "v1v2_hdmi";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ interrupts = <IT_CURLIM_LDO6 0>;
+ };
+
+ vref_ddr: vref_ddr {
+ regulator-name = "vref_ddr";
+ regulator-always-on;
+ regulator-over-current-protection;
+ };
+
+ bst_out: boost {
+ regulator-name = "bst_out";
+ interrupts = <IT_OCP_BOOST 0>;
+ };
+
+ vbus_otg: pwr_sw1 {
+ regulator-name = "vbus_otg";
+ interrupts = <IT_OCP_OTG 0>;
+ };
+
+ vbus_sw: pwr_sw2 {
+ regulator-name = "vbus_sw";
+ interrupts = <IT_OCP_SWOUT 0>;
+ regulator-active-discharge = <1>;
+ };
+ };
+
+ onkey {
+ compatible = "st,stpmic1-onkey";
+ interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
+ interrupt-names = "onkey-falling", "onkey-rising";
+ power-off-time-sec = <10>;
+ status = "okay";
+ };
+
+ watchdog {
+ compatible = "st,stpmic1-wdt";
+ status = "disabled";
+ };
+ };
+};
+
+&i2s2 {
+ clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
+ clock-names = "pclk", "i2sclk", "x8k", "x11k";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2s2_pins_a>;
+ pinctrl-1 = <&i2s2_pins_sleep_a>;
+ status = "okay";
+
+ i2s2_port: port {
+ i2s2_endpoint: endpoint {
+ remote-endpoint = <&sii9022_tx_endpoint>;
+ format = "i2s";
+ mclk-fs = <256>;
+ };
+ };
+};
+
+&ipcc {
+ status = "okay";
+};
+
+&iwdg2 {
+ timeout-sec = <32>;
+ status = "okay";
+};
+
+&ltdc {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&ltdc_pins_a>;
+ pinctrl-1 = <&ltdc_pins_sleep_a>;
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ltdc_ep0_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&sii9022_in>;
+ };
+ };
+};
+
+&m4_rproc {
+ memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
+ <&vdev0vring1>, <&vdev0buffer>;
+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
+ mbox-names = "vq0", "vq1", "shutdown";
+ interrupt-parent = <&exti>;
+ interrupts = <68 1>;
+ status = "okay";
+};
+
+&pwr_regulators {
+ vdd-supply = <&vdd>;
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
+};
+
+&rng1 {
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sai2 {
+ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
+ clock-names = "pclk", "x8k", "x11k";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_b>;
+ pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_b>;
+ status = "okay";
+
+ sai2a: audio-controller@4400b004 {
+ #clock-cells = <0>;
+ dma-names = "tx";
+ clocks = <&rcc SAI2_K>;
+ clock-names = "sai_ck";
+ status = "okay";
+
+ sai2a_port: port {
+ sai2a_endpoint: endpoint {
+ remote-endpoint = <&cs42l51_tx_endpoint>;
+ format = "i2s";
+ mclk-fs = <256>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <32>;
+ };
+ };
+ };
+
+ sai2b: audio-controller@4400b024 {
+ dma-names = "rx";
+ st,sync = <&sai2a 2>;
+ clocks = <&rcc SAI2_K>, <&sai2a>;
+ clock-names = "sai_ck", "MCLK";
+ status = "okay";
+
+ sai2b_port: port {
+ sai2b_endpoint: endpoint {
+ remote-endpoint = <&cs42l51_rx_endpoint>;
+ format = "i2s";
+ mclk-fs = <256>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <32>;
+ };
+ };
+ };
+};
+
+&sdmmc1 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+ broken-cd;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&v3v3>;
+ status = "okay";
+};
+
+&sdmmc3 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc3_b4_pins_a>;
+ pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
+ broken-cd;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&v3v3>;
+ status = "disabled";
+};
+
+&timers1 {
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm1_pins_a>;
+ pinctrl-1 = <&pwm1_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@0 {
+ status = "okay";
+ };
+};
+
+&timers3 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm3_pins_a>;
+ pinctrl-1 = <&pwm3_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@2 {
+ status = "okay";
+ };
+};
+
+&timers4 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm4_pins_a &pwm4_pins_b>;
+ pinctrl-1 = <&pwm4_sleep_pins_a &pwm4_sleep_pins_b>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@3 {
+ status = "okay";
+ };
+};
+
+&timers5 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm5_pins_a>;
+ pinctrl-1 = <&pwm5_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@4 {
+ status = "okay";
+ };
+};
+
+&timers6 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ timer@5 {
+ status = "okay";
+ };
+};
+
+&timers12 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm12_pins_a>;
+ pinctrl-1 = <&pwm12_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@11 {
+ status = "okay";
+ };
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_a>;
+ status = "okay";
+};
+
+&usbh_ehci {
+ phys = <&usbphyc_port0>;
+ status = "okay";
+};
+
+&usbotg_hs {
+ dr_mode = "peripheral";
+ phys = <&usbphyc_port1 0>;
+ phy-names = "usb2-phy";
+ status = "okay";
+};
+
+&usbphyc {
+ status = "okay";
+};
+
+&usbphyc_port0 {
+ phy-supply = <&vdd_usb>;
+ vdda1v1-supply = <&reg11>;
+ vdda1v8-supply = <&reg18>;
+};
+
+&usbphyc_port1 {
+ phy-supply = <&vdd_usb>;
+ vdda1v1-supply = <&reg11>;
+ vdda1v8-supply = <&reg18>;
+};
+
+&vrefbuf {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ vdda-supply = <&vdd>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32mp15xxaa-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15xxaa-pinctrl.dtsi
new file mode 100644
index 000000000000..04f7a43ad66f
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xxaa-pinctrl.dtsi
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+&pinctrl {
+ st,package = <STM32MP_PKG_AA>;
+
+ gpioa: gpio@50002000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@50003000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@50004000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ gpiod: gpio@50005000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@50006000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@50007000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@50008000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@50009000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 112 16>;
+ };
+
+ gpioi: gpio@5000a000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 128 16>;
+ };
+
+ gpioj: gpio@5000b000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 144 16>;
+ };
+
+ gpiok: gpio@5000c000 {
+ status = "okay";
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl 0 160 8>;
+ };
+};
+
+&pinctrl_z {
+ st,package = <STM32MP_PKG_AA>;
+
+ gpioz: gpio@54004000 {
+ status = "okay";
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl_z 0 400 8>;
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp15xxab-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15xxab-pinctrl.dtsi
new file mode 100644
index 000000000000..328dad140e9b
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xxab-pinctrl.dtsi
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+&pinctrl {
+ st,package = <STM32MP_PKG_AB>;
+
+ gpioa: gpio@50002000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@50003000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@50004000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ gpiod: gpio@50005000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@50006000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@50007000 {
+ status = "okay";
+ ngpios = <6>;
+ gpio-ranges = <&pinctrl 6 86 6>;
+ };
+
+ gpiog: gpio@50008000 {
+ status = "okay";
+ ngpios = <10>;
+ gpio-ranges = <&pinctrl 6 102 10>;
+ };
+
+ gpioh: gpio@50009000 {
+ status = "okay";
+ ngpios = <2>;
+ gpio-ranges = <&pinctrl 0 112 2>;
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp15xxac-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15xxac-pinctrl.dtsi
new file mode 100644
index 000000000000..7eaa245f44db
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xxac-pinctrl.dtsi
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+&pinctrl {
+ st,package = <STM32MP_PKG_AC>;
+
+ gpioa: gpio@50002000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@50003000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@50004000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ gpiod: gpio@50005000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@50006000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@50007000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@50008000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@50009000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 112 16>;
+ };
+
+ gpioi: gpio@5000a000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 0 128 12>;
+ };
+};
+
+&pinctrl_z {
+ st,package = <STM32MP_PKG_AC>;
+
+ gpioz: gpio@54004000 {
+ status = "okay";
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl_z 0 400 8>;
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp15xxad-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15xxad-pinctrl.dtsi
new file mode 100644
index 000000000000..b63e207de216
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xxad-pinctrl.dtsi
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+&pinctrl {
+ st,package = <STM32MP_PKG_AD>;
+
+ gpioa: gpio@50002000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@50003000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@50004000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ gpiod: gpio@50005000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@50006000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@50007000 {
+ status = "okay";
+ ngpios = <6>;
+ gpio-ranges = <&pinctrl 6 86 6>;
+ };
+
+ gpiog: gpio@50008000 {
+ status = "okay";
+ ngpios = <10>;
+ gpio-ranges = <&pinctrl 6 102 10>;
+ };
+
+ gpioh: gpio@50009000 {
+ status = "okay";
+ ngpios = <2>;
+ gpio-ranges = <&pinctrl 0 112 2>;
+ };
+};
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 4c268b70b735..bf531efc0610 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -624,6 +624,16 @@
status = "disabled";
};
+ csi1: csi@1c1d000 {
+ compatible = "allwinner,sun4i-a10-csi1";
+ reg = <0x01c1d000 0x1000>;
+ interrupts = <43>;
+ clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
+ clock-names = "bus", "ram";
+ resets = <&ccu RST_CSI1>;
+ status = "disabled";
+ };
+
spi3: spi@1c1f000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c1f000 0x1000>;
@@ -670,6 +680,31 @@
function = "can";
};
+ /omit-if-no-ref/
+ csi1_8bits_pg_pins: csi1-8bits-pg-pins {
+ pins = "PG0", "PG2", "PG3", "PG4", "PG5",
+ "PG6", "PG7", "PG8", "PG9", "PG10",
+ "PG11";
+ function = "csi1";
+ };
+
+ /omit-if-no-ref/
+ csi1_24bits_ph_pins: csi1-24bits-ph-pins {
+ pins = "PH0", "PH1", "PH2", "PH3", "PH4",
+ "PH5", "PH6", "PH7", "PH8", "PH9",
+ "PH10", "PH11", "PH12", "PH13", "PH14",
+ "PH15", "PH16", "PH17", "PH18", "PH19",
+ "PH20", "PH21", "PH22", "PH23", "PH24",
+ "PH25", "PH26", "PH27";
+ function = "csi1";
+ };
+
+ /omit-if-no-ref/
+ csi1_clk_pg_pin: csi1-clk-pg-pin {
+ pins = "PG1";
+ function = "csi1";
+ };
+
emac_pins: emac0-pins {
pins = "PA0", "PA1", "PA2",
"PA3", "PA4", "PA5", "PA6",
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 6befa236ba99..0b526e6e5a95 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -185,7 +185,7 @@
mbus: dram-controller@1c01000 {
compatible = "allwinner,sun5i-a13-mbus";
reg = <0x01c01000 0x1000>;
- clocks = <&ccu 99>;
+ clocks = <&ccu CLK_MBUS>;
dma-ranges = <0x00000000 0x40000000 0x20000000>;
#interconnect-cells = <1>;
};
@@ -275,6 +275,7 @@
compatible = "allwinner,sun5i-a13-tcon";
reg = <0x01c0c000 0x1000>;
interrupts = <44>;
+ dmas = <&dma SUN4I_DMA_DEDICATED 14>;
resets = <&ccu RST_LCD>;
reset-names = "lcd";
clocks = <&ccu CLK_AHB_LCD>,
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 2cf34ae1c17b..7762fbd9a133 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -285,14 +285,19 @@
compatible = "allwinner,sun6i-a31-tcon";
reg = <0x01c0c000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&ccu RST_AHB1_LCD0>;
- reset-names = "lcd";
+ dmas = <&dma 11>;
+ resets = <&ccu RST_AHB1_LCD0>,
+ <&ccu RST_AHB1_LVDS>;
+ reset-names = "lcd",
+ "lvds";
clocks = <&ccu CLK_AHB1_LCD0>,
<&ccu CLK_LCD0_CH0>,
- <&ccu CLK_LCD0_CH1>;
+ <&ccu CLK_LCD0_CH1>,
+ <&ccu 15>;
clock-names = "ahb",
"tcon-ch0",
- "tcon-ch1";
+ "tcon-ch1",
+ "lvds-alt";
clock-output-names = "tcon0-pixel-clock";
#clock-cells = <0>;
@@ -334,14 +339,18 @@
compatible = "allwinner,sun6i-a31-tcon";
reg = <0x01c0d000 0x1000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&ccu RST_AHB1_LCD1>;
- reset-names = "lcd";
+ dmas = <&dma 12>;
+ resets = <&ccu RST_AHB1_LCD1>,
+ <&ccu RST_AHB1_LVDS>;
+ reset-names = "lcd", "lvds";
clocks = <&ccu CLK_AHB1_LCD1>,
<&ccu CLK_LCD1_CH0>,
- <&ccu CLK_LCD1_CH1>;
+ <&ccu CLK_LCD1_CH1>,
+ <&ccu 15>;
clock-names = "ahb",
"tcon-ch0",
- "tcon-ch1";
+ "tcon-ch1",
+ "lvds-alt";
clock-output-names = "tcon1-pixel-clock";
#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 8aebefd6accf..92b5be97085d 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -729,6 +729,17 @@
status = "disabled";
};
+ csi1: csi@1c1d000 {
+ compatible = "allwinner,sun7i-a20-csi1",
+ "allwinner,sun4i-a10-csi1";
+ reg = <0x01c1d000 0x1000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
+ clock-names = "bus", "ram";
+ resets = <&ccu RST_CSI1>;
+ status = "disabled";
+ };
+
spi3: spi@1c1f000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c1f000 0x1000>;
@@ -803,6 +814,31 @@
};
/omit-if-no-ref/
+ csi1_8bits_pg_pins: csi1-8bits-pg-pins {
+ pins = "PG0", "PG2", "PG3", "PG4", "PG5",
+ "PG6", "PG7", "PG8", "PG9", "PG10",
+ "PG11";
+ function = "csi1";
+ };
+
+ /omit-if-no-ref/
+ csi1_24bits_ph_pins: csi1-24bits-ph-pins {
+ pins = "PH0", "PH1", "PH2", "PH3", "PH4",
+ "PH5", "PH6", "PH7", "PH8", "PH9",
+ "PH10", "PH11", "PH12", "PH13", "PH14",
+ "PH15", "PH16", "PH17", "PH18", "PH19",
+ "PH20", "PH21", "PH22", "PH23", "PH24",
+ "PH25", "PH26", "PH27";
+ function = "csi1";
+ };
+
+ /omit-if-no-ref/
+ csi1_clk_pg_pin: csi1-clk-pg-pin {
+ pins = "PG1";
+ function = "csi1";
+ };
+
+ /omit-if-no-ref/
emac_pa_pins: emac-pa-pins {
pins = "PA0", "PA1", "PA2",
"PA3", "PA4", "PA5", "PA6",
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index f292f96ab39b..48487f6d4ab9 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -182,14 +182,19 @@
/* compatible gets set in SoC specific dtsi file */
reg = <0x01c0c000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma 12>;
clocks = <&ccu CLK_BUS_LCD>,
- <&ccu CLK_LCD_CH0>;
+ <&ccu CLK_LCD_CH0>,
+ <&ccu 13>;
clock-names = "ahb",
- "tcon-ch0";
+ "tcon-ch0",
+ "lvds-alt";
clock-output-names = "tcon-pixel-clock";
#clock-cells = <0>;
- resets = <&ccu RST_BUS_LCD>;
- reset-names = "lcd";
+ resets = <&ccu RST_BUS_LCD>,
+ <&ccu RST_BUS_LVDS>;
+ reset-names = "lcd",
+ "lvds";
status = "disabled";
ports {
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 53c38deb8a08..74ac7ee9383c 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -50,6 +50,7 @@
#include <dt-bindings/reset/sun8i-a83t-ccu.h>
#include <dt-bindings/reset/sun8i-de2.h>
#include <dt-bindings/reset/sun8i-r-ccu.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&gic>;
@@ -581,6 +582,12 @@
sid: eeprom@1c14000 {
compatible = "allwinner,sun8i-a83t-sid";
reg = <0x1c14000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ths_calibration: thermal-sensor-calibration@34 {
+ reg = <0x34 8>;
+ };
};
crypto: crypto@1c15000 {
@@ -999,9 +1006,9 @@
reg = <0x01c30000 0x104>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
- resets = <&ccu 13>;
+ resets = <&ccu CLK_BUS_EMAC>;
reset-names = "stmmaceth";
- clocks = <&ccu 27>;
+ clocks = <&ccu RST_BUS_EMAC>;
clock-names = "stmmaceth";
status = "disabled";
@@ -1095,7 +1102,7 @@
compatible = "allwinner,sun8i-a83t-r-ccu";
reg = <0x01f01400 0x400>;
clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
- <&ccu 6>;
+ <&ccu CLK_PLL_PERIPH>;
clock-names = "hosc", "losc", "iosc", "pll-periph";
#clock-cells = <1>;
#reset-cells = <1>;
@@ -1165,5 +1172,34 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+ ths: thermal-sensor@1f04000 {
+ compatible = "allwinner,sun8i-a83t-ths";
+ reg = <0x01f04000 0x100>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ nvmem-cells = <&ths_calibration>;
+ nvmem-cell-names = "calibration";
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ thermal-zones {
+ cpu0_thermal: cpu0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths 0>;
+ };
+
+ cpu1_thermal: cpu1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths 1>;
+ };
+
+ gpu_thermal: gpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths 2>;
+ };
};
};
diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
index ac9e26b1d906..45a24441ff18 100644
--- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
@@ -143,6 +143,7 @@
};
&ir {
+ linux,rc-map-name = "rc-tanix-tx3mini";
pinctrl-names = "default";
pinctrl-0 = <&r_ir_rx_pin>;
status = "okay";
diff --git a/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3-devboard.dts b/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3-devboard.dts
new file mode 100644
index 000000000000..02fbe00cde97
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3-devboard.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * DTS for Emlid Neutis N5 Dev board.
+ *
+ * Copyright (C) 2019 Georgii Staroselskii <georgiii.staroselskii@emlid.com>
+ */
+
+/dts-v1/;
+
+#include "sun8i-h3-emlid-neutis-n5h3.dtsi"
+
+/ {
+ model = "Emlid Neutis N5H3 Developer board";
+ compatible = "emlid,neutis-n5h3-devboard",
+ "emlid,neutis-n5h3",
+ "allwinner,sun8i-h3";
+
+ vdd_cpux: gpio-regulator {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd-cpux";
+ regulator-type = "voltage";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-ramp-delay = <50>; /* 4ms */
+ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
+ gpios-states = <0x1>;
+ states = <1100000 0x0>, <1300000 0x1>;
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpux>;
+};
+
+&codec {
+ status = "okay";
+};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi b/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi
new file mode 100644
index 000000000000..eedd5da5dc2f
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * DTSI for Emlid Neutis N5 SoM.
+ *
+ * Copyright (C) 2019 Georgii Staroselskii <georgii.staroselskii@emlid.com>
+ */
+
+/dts-v1/;
+
+#include "sun8i-h3.dtsi"
+#include <arm/sunxi-h3-h5-emlid-neutis.dtsi>
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts
index c73f59900975..6b149271ef13 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts
@@ -60,8 +60,7 @@
enable-gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
gpios-states = <0x1>;
- states = <1100000 0x0
- 1300000 0x1>;
+ states = <1100000 0>, <1300000 1>;
};
reg_vcc_dram: vcc-dram {
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index fe773c72a69b..20217e2ca4d3 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -80,7 +80,7 @@
#cooling-cells = <2>;
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <1>;
@@ -90,7 +90,7 @@
#cooling-cells = <2>;
};
- cpu@2 {
+ cpu2: cpu@2 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <2>;
@@ -100,7 +100,7 @@
#cooling-cells = <2>;
};
- cpu@3 {
+ cpu3: cpu@3 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <3>;
@@ -111,6 +111,15 @@
};
};
+ pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@@ -199,6 +208,26 @@
assigned-clocks = <&ccu CLK_GPU>;
assigned-clock-rates = <384000000>;
};
+
+ ths: thermal-sensor@1c25000 {
+ compatible = "allwinner,sun8i-h3-ths";
+ reg = <0x01c25000 0x400>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ccu RST_BUS_THS>;
+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
+ clock-names = "bus", "mod";
+ nvmem-cells = <&ths_calibration>;
+ nvmem-cell-names = "calibration";
+ #thermal-sensor-cells = <0>;
+ };
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths 0>;
+ };
};
};
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 421dfbbfd7ee..8f09a24b36ec 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -44,6 +44,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun8i-de2.h>
#include <dt-bindings/clock/sun8i-r40-ccu.h>
+#include <dt-bindings/clock/sun8i-tcon-top.h>
#include <dt-bindings/reset/sun8i-r40-ccu.h>
#include <dt-bindings/reset/sun8i-de2.h>
@@ -78,25 +79,25 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <1>;
};
- cpu@2 {
+ cpu2: cpu@2 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <2>;
};
- cpu@3 {
+ cpu3: cpu@3 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <3>;
@@ -180,6 +181,20 @@
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
+ csi0: csi@1c09000 {
+ compatible = "allwinner,sun8i-r40-csi0",
+ "allwinner,sun7i-a20-csi0";
+ reg = <0x01c09000 0x1000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>,
+ <&ccu CLK_DRAM_CSI0>;
+ clock-names = "bus", "isp", "ram";
+ resets = <&ccu RST_BUS_CSI0>;
+ interconnects = <&mbus 5>;
+ interconnect-names = "dma-mem";
+ status = "disabled";
+ };
+
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun8i-r40-mmc",
"allwinner,sun50i-a64-mmc";
@@ -355,6 +370,20 @@
function = "clk_out_a";
};
+ /omit-if-no-ref/
+ csi0_8bits_pins: csi0-8bits-pins {
+ pins = "PE0", "PE2", "PE3", "PE4", "PE5",
+ "PE6", "PE7", "PE8", "PE9", "PE10",
+ "PE11";
+ function = "csi0";
+ };
+
+ /omit-if-no-ref/
+ csi0_mclk_pin: csi0-mclk-pin {
+ pins = "PE1";
+ function = "csi0";
+ };
+
gmac_rgmii_pins: gmac-rgmii-pins {
pins = "PA0", "PA1", "PA2", "PA3",
"PA4", "PA5", "PA6", "PA7",
@@ -373,6 +402,26 @@
function = "i2c0";
};
+ i2c1_pins: i2c1-pins {
+ pins = "PB18", "PB19";
+ function = "i2c1";
+ };
+
+ i2c2_pins: i2c2-pins {
+ pins = "PB20", "PB21";
+ function = "i2c2";
+ };
+
+ i2c3_pins: i2c3-pins {
+ pins = "PI0", "PI1";
+ function = "i2c3";
+ };
+
+ i2c4_pins: i2c4-pins {
+ pins = "PI2", "PI3";
+ function = "i2c4";
+ };
+
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
@@ -398,6 +447,36 @@
bias-pull-up;
};
+ /omit-if-no-ref/
+ spi0_pc_pins: spi0-pc-pins {
+ pins = "PC0", "PC1", "PC2";
+ function = "spi0";
+ };
+
+ /omit-if-no-ref/
+ spi0_cs0_pc_pin: spi0-cs0-pc-pin {
+ pins = "PC23";
+ function = "spi0";
+ };
+
+ /omit-if-no-ref/
+ spi1_pi_pins: spi1-pi-pins {
+ pins = "PI17", "PI18", "PI19";
+ function = "spi1";
+ };
+
+ /omit-if-no-ref/
+ spi1_cs0_pi_pin: spi1-cs0-pi-pin {
+ pins = "PI16";
+ function = "spi1";
+ };
+
+ /omit-if-no-ref/
+ spi1_cs1_pi_pin: spi1-cs1-pi-pin {
+ pins = "PI15";
+ function = "spi1";
+ };
+
uart0_pb_pins: uart0-pb-pins {
pins = "PB22", "PB23";
function = "uart0";
@@ -528,6 +607,8 @@
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C1>;
resets = <&ccu RST_BUS_I2C1>;
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -539,6 +620,8 @@
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C2>;
resets = <&ccu RST_BUS_I2C2>;
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -550,6 +633,8 @@
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C3>;
resets = <&ccu RST_BUS_I2C3>;
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-names = "default";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -561,6 +646,60 @@
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C4>;
resets = <&ccu RST_BUS_I2C4>;
+ pinctrl-0 = <&i2c4_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi0: spi@1c05000 {
+ compatible = "allwinner,sun8i-r40-spi",
+ "allwinner,sun8i-h3-spi";
+ reg = <0x01c05000 0x1000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi@1c06000 {
+ compatible = "allwinner,sun8i-r40-spi",
+ "allwinner,sun8i-h3-spi";
+ reg = <0x01c06000 0x1000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi2: spi@1c07000 {
+ compatible = "allwinner,sun8i-r40-spi",
+ "allwinner,sun8i-h3-spi";
+ reg = <0x01c07000 0x1000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI2>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi3: spi@1c0f000 {
+ compatible = "allwinner,sun8i-r40-spi",
+ "allwinner,sun8i-h3-spi";
+ reg = <0x01c0f000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI3>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -596,6 +735,14 @@
};
};
+ mbus: dram-controller@1c62000 {
+ compatible = "allwinner,sun8i-r40-mbus";
+ reg = <0x01c62000 0x1000>;
+ clocks = <&ccu 155>;
+ dma-ranges = <0x00000000 0x40000000 0x80000000>;
+ #interconnect-cells = <1>;
+ };
+
tcon_top: tcon-top@1c70000 {
compatible = "allwinner,sun8i-r40-tcon-top";
reg = <0x01c70000 0x1000>;
@@ -718,7 +865,7 @@
compatible = "allwinner,sun8i-r40-tcon-tv";
reg = <0x01c73000 0x1000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>;
+ clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>;
clock-names = "ahb", "tcon-ch1";
resets = <&ccu RST_BUS_TCON_TV0>;
reset-names = "lcd";
@@ -761,7 +908,7 @@
compatible = "allwinner,sun8i-r40-tcon-tv";
reg = <0x01c74000 0x1000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>;
+ clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>;
clock-names = "ahb", "tcon-ch1";
resets = <&ccu RST_BUS_TCON_TV1>;
reset-names = "lcd";
@@ -803,7 +950,7 @@
gic: interrupt-controller@1c81000 {
compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
- <0x01c82000 0x1000>,
+ <0x01c82000 0x2000>,
<0x01c84000 0x2000>,
<0x01c86000 0x2000>;
interrupt-controller;
@@ -848,7 +995,7 @@
compatible = "allwinner,sun8i-r40-hdmi-phy";
reg = <0x01ef0000 0x10000>;
clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
- <&ccu 7>, <&ccu 16>;
+ <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>;
clock-names = "bus", "mod", "pll-0", "pll-1";
resets = <&ccu RST_BUS_HDMI0>;
reset-names = "phy";
@@ -856,6 +1003,15 @@
};
};
+ pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 23ba56df38f7..81ea50838cd5 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -123,8 +123,6 @@
clock-names = "bus",
"mod";
resets = <&display_clocks 0>;
- assigned-clocks = <&display_clocks 6>;
- assigned-clock-rates = <150000000>;
ports {
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 1d900f591d5f..ce4fa6706d06 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -387,16 +387,16 @@
usbphy2: phy@a01800 {
compatible = "allwinner,sun9i-a80-usb-phy";
reg = <0x00a01800 0x4>;
- clocks = <&usb_clocks CLK_USB1_HSIC>,
+ clocks = <&usb_clocks CLK_USB1_PHY>,
<&usb_clocks CLK_USB_HSIC>,
- <&usb_clocks CLK_USB1_PHY>;
- clock-names = "hsic_480M",
+ <&usb_clocks CLK_USB1_HSIC>;
+ clock-names = "phy",
"hsic_12M",
- "phy";
- resets = <&usb_clocks RST_USB1_HSIC>,
- <&usb_clocks RST_USB1_PHY>;
- reset-names = "hsic",
- "phy";
+ "hsic_480M";
+ resets = <&usb_clocks RST_USB1_PHY>,
+ <&usb_clocks RST_USB1_HSIC>;
+ reset-names = "phy",
+ "hsic";
status = "disabled";
#phy-cells = <0>;
/* usb1 is always used with HSIC */
@@ -429,16 +429,16 @@
usbphy3: phy@a02800 {
compatible = "allwinner,sun9i-a80-usb-phy";
reg = <0x00a02800 0x4>;
- clocks = <&usb_clocks CLK_USB2_HSIC>,
+ clocks = <&usb_clocks CLK_USB2_PHY>,
<&usb_clocks CLK_USB_HSIC>,
- <&usb_clocks CLK_USB2_PHY>;
- clock-names = "hsic_480M",
+ <&usb_clocks CLK_USB2_HSIC>;
+ clock-names = "phy",
"hsic_12M",
- "phy";
- resets = <&usb_clocks RST_USB2_HSIC>,
- <&usb_clocks RST_USB2_PHY>;
- reset-names = "hsic",
- "phy";
+ "hsic_480M";
+ resets = <&usb_clocks RST_USB2_PHY>,
+ <&usb_clocks RST_USB2_HSIC>;
+ reset-names = "phy",
+ "hsic";
status = "disabled";
#phy-cells = <0>;
};
@@ -530,9 +530,7 @@
compatible = "allwinner,sun9i-a80-mmc-config-clk";
reg = <0x01c13000 0x10>;
clocks = <&ccu CLK_BUS_MMC>;
- clock-names = "ahb";
resets = <&ccu RST_BUS_MMC>;
- reset-names = "ahb";
#clock-cells = <1>;
#reset-cells = <1>;
clock-output-names = "mmc0_config", "mmc1_config",
@@ -880,8 +878,12 @@
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>;
clock-names = "ahb", "tcon-ch0";
- resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>;
- reset-names = "lcd", "edp";
+ resets = <&ccu RST_BUS_LCD0>,
+ <&ccu RST_BUS_EDP>,
+ <&ccu RST_BUS_LVDS>;
+ reset-names = "lcd",
+ "edp",
+ "lvds";
clock-output-names = "tcon0-pixel-clock";
#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi b/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi
new file mode 100644
index 000000000000..fc67e30fe212
--- /dev/null
+++ b/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * DTSI for Emlid Neutis SoMs.
+ *
+ * Copyright (C) 2019 Georgii Staroselskii <georgii.staroselskii@emlid.com>
+ */
+
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */
+ post-power-on-delay-ms = <200>;
+ clocks = <&rtc 1>;
+ clock-names = "ext_clock";
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpux>;
+};
+
+&reg_usb0_vbus {
+ gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
+ status = "okay";
+};
+
+
+&de {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&mmc0 {
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+
+&mmc1 {
+ vmmc-supply = <&reg_vcc3v3>;
+ vqmmc-supply = <&reg_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 5 IRQ_TYPE_LEVEL_LOW>; /* PL5 */
+ interrupt-names = "host-wake";
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rtc 1>;
+ clock-names = "lpo";
+ vbat-supply = <&reg_vcc3v3>;
+ vddio-supply = <&reg_vcc3v3>;
+ shutdown-gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */
+ device-wakeup-gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
+ usb0_vbus-supply = <&reg_usb0_vbus>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "LINEIN", "Line In",
+ "MIC1", "Mic",
+ "MIC2", "Mic",
+ "Mic", "MBIAS";
+};
+
+&i2c0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 0afea59486c2..5e9c3060aa08 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -231,6 +231,12 @@
sid: eeprom@1c14000 {
/* compatible is in per SoC .dtsi file */
reg = <0x1c14000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ths_calibration: thermal-sensor-calibration@34 {
+ reg = <0x34 4>;
+ };
};
usb_otg: usb@1c19000 {
@@ -553,7 +559,7 @@
mbus: dram-controller@1c62000 {
compatible = "allwinner,sun8i-h3-mbus";
reg = <0x01c62000 0x1000>;
- clocks = <&ccu 113>;
+ clocks = <&ccu CLK_MBUS>;
dma-ranges = <0x00000000 0x40000000 0xc0000000>;
#interconnect-cells = <1>;
};
@@ -811,7 +817,7 @@
compatible = "allwinner,sun8i-h3-hdmi-phy";
reg = <0x01ef0000 0x10000>;
clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
- <&ccu 6>;
+ <&ccu CLK_PLL_VIDEO>;
clock-names = "bus", "mod", "pll-0";
resets = <&ccu RST_BUS_HDMI0>;
reset-names = "phy";
@@ -831,7 +837,8 @@
r_ccu: clock@1f01400 {
compatible = "allwinner,sun8i-h3-r-ccu";
reg = <0x01f01400 0x100>;
- clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 9>;
+ clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
+ <&ccu CLK_PLL_PERIPH0>;
clock-names = "hosc", "losc", "iosc", "pll-periph";
#clock-cells = <1>;
#reset-cells = <1>;
diff --git a/arch/arm/boot/dts/sunxi-libretech-all-h3-it.dtsi b/arch/arm/boot/dts/sunxi-libretech-all-h3-it.dtsi
new file mode 100644
index 000000000000..204fba3614f9
--- /dev/null
+++ b/arch/arm/boot/dts/sunxi-libretech-all-h3-it.dtsi
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2019 Chen-Yu Tsai <wens@csie.org>
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ aliases {
+ serial0 = &uart0;
+ spi0 = &spi0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "d";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status_led {
+ label = "librecomputer:blue:status";
+ gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */
+ };
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&reg_vcc5v0>;
+ };
+
+ /* This represents the board's 5V input */
+ reg_vcc5v0: vcc5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reg_vcc_dram: vcc-dram {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-dram";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&reg_vcc5v0>;
+ gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
+ enable-active-high;
+ };
+
+ reg_vcc_io: vcc-io {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-io";
+ /* This is simply a MOSFET switch */
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&reg_vcc3v3>;
+ gpio = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */
+ };
+
+ reg_vcc_usbwifi: vcc-usbwifi {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-usbwifi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&reg_vcc5v0>;
+ gpio = <&pio 6 4 GPIO_ACTIVE_HIGH>; /* PG4 */
+ enable-active-high;
+ };
+
+ reg_vdd_cpux: vdd-cpux {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-cpux";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&reg_vcc5v0>;
+ gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
+ enable-active-high;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_vdd_cpux>;
+};
+
+&cpu1 {
+ cpu-supply = <&reg_vdd_cpux>;
+};
+
+&cpu2 {
+ cpu-supply = <&reg_vdd_cpux>;
+};
+
+&cpu3 {
+ cpu-supply = <&reg_vdd_cpux>;
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <&reg_vcc_io>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&pio {
+ vcc-pa-supply = <&reg_vcc_io>;
+ vcc-pc-supply = <&reg_vcc_io>;
+ vcc-pd-supply = <&reg_vcc_io>;
+ vcc-pe-supply = <&reg_vcc_io>;
+ vcc-pf-supply = <&reg_vcc_io>;
+ vcc-pg-supply = <&reg_vcc_io>;
+};
+
+&r_pio {
+ vcc-pl-supply = <&reg_vcc3v3>;
+};
+
+&spi0 {
+ status = "okay";
+
+ spiflash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <&reg_vcc_usbwifi>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi
index d18eaf4a4a3a..32401457ae71 100644
--- a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi
@@ -84,7 +84,7 @@
};
};
- emc@7001b000 {
+ external-memory-controller@7001b000 {
emc-timings-1 {
nvidia,ram-code = <1>;
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi
index 784a529e1f19..861d3f22116b 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi
@@ -79,7 +79,7 @@
};
};
- emc@7001b000 {
+ external-memory-controller@7001b000 {
emc-timings-3 {
nvidia,ram-code = <3>;
diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi
index fb6b3e1a0b1f..c91647d13a50 100644
--- a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi
@@ -219,7 +219,7 @@
};
};
- emc@7001b000 {
+ external-memory-controller@7001b000 {
emc-timings-1 {
nvidia,ram-code = <1>;
diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi
index c7c31d4c1a2b..d2beea0bd15f 100644
--- a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi
@@ -68,7 +68,7 @@
};
};
- emc@7001b000 {
+ external-memory-controller@7001b000 {
emc-timings-1 {
nvidia,ram-code = <1>;
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 413bfb981de8..7f330b1f150f 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -622,9 +622,11 @@
#iommu-cells = <1>;
};
- emc: emc@7001b000 {
+ emc: external-memory-controller@7001b000 {
compatible = "nvidia,tegra124-emc";
reg = <0x0 0x7001b000 0x0 0x1000>;
+ clocks = <&tegra_car TEGRA124_CLK_EMC>;
+ clock-names = "emc";
nvidia,memory-controller = <&mc>;
};
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 85fce5bc72d6..be0ab9b84b9a 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -311,6 +311,52 @@
reset-names = "i2c";
};
+ memory-controller@7000f400 {
+ nvidia,use-ram-code;
+
+ emc-tables@hynix {
+ nvidia,ram-code = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ emc-table@166500 {
+ reg = <166500>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <166500>;
+ nvidia,emc-registers = <0x0000000a 0x00000016
+ 0x00000008 0x00000003 0x00000004 0x00000004
+ 0x00000002 0x0000000c 0x00000003 0x00000003
+ 0x00000002 0x00000001 0x00000004 0x00000005
+ 0x00000004 0x00000009 0x0000000d 0x000004df
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000003 0x00000001 0x0000000a 0x000000c8
+ 0x00000003 0x00000006 0x00000004 0x00000008
+ 0x00000002 0x00000000 0x00000000 0x00000002
+ 0x00000000 0x00000000 0x00000083 0xe03b0323
+ 0x007fe010 0x00001414 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+
+ emc-table@333000 {
+ reg = <333000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <333000>;
+ nvidia,emc-registers = <0x00000018 0x00000033
+ 0x00000012 0x00000004 0x00000004 0x00000005
+ 0x00000003 0x0000000c 0x00000006 0x00000006
+ 0x00000003 0x00000001 0x00000004 0x00000005
+ 0x00000004 0x00000009 0x0000000d 0x00000bff
+ 0x00000000 0x00000003 0x00000003 0x00000006
+ 0x00000006 0x00000001 0x00000011 0x000000c8
+ 0x00000003 0x0000000e 0x00000007 0x00000008
+ 0x00000002 0x00000000 0x00000000 0x00000002
+ 0x00000000 0x00000000 0x00000083 0xf0440303
+ 0x007fe010 0x00001414 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+ };
+ };
+
i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi
index 58cd4e8fa5be..64ec46c72a4c 100644
--- a/arch/arm/boot/dts/uniphier-ld4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ld4.dtsi
@@ -410,7 +410,8 @@
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
- resets = <&sys_rst 2>;
+ reset-names = "nand", "reg";
+ resets = <&sys_rst 2>, <&sys_rst 2>;
};
};
};
diff --git a/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/uniphier-pinctrl.dtsi
index 1fee5ffbfb9c..bfdfb764b25b 100644
--- a/arch/arm/boot/dts/uniphier-pinctrl.dtsi
+++ b/arch/arm/boot/dts/uniphier-pinctrl.dtsi
@@ -106,6 +106,16 @@
function = "i2c4";
};
+ pinctrl_i2c5: i2c5 {
+ groups = "i2c5";
+ function = "i2c5";
+ };
+
+ pinctrl_i2c6: i2c6 {
+ groups = "i2c6";
+ function = "i2c6";
+ };
+
pinctrl_nand: nand {
groups = "nand";
function = "nand";
diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi
index 7f64e5a616d6..2ec04d7972ef 100644
--- a/arch/arm/boot/dts/uniphier-pro4.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro4.dtsi
@@ -600,7 +600,8 @@
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
- resets = <&sys_rst 2>;
+ reset-names = "nand", "reg";
+ resets = <&sys_rst 2>, <&sys_rst 2>;
};
};
};
diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
index eff74717b37c..ea3961f920a0 100644
--- a/arch/arm/boot/dts/uniphier-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
@@ -465,7 +465,8 @@
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
- resets = <&sys_rst 2>;
+ reset-names = "nand", "reg";
+ resets = <&sys_rst 2>, <&sys_rst 2>;
};
emmc: sdhc@68400000 {
diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index 4eddbb8d7fca..13b0d4a7741f 100644
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -773,7 +773,8 @@
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
- resets = <&sys_rst 2>;
+ reset-names = "nand", "reg";
+ resets = <&sys_rst 2>, <&sys_rst 2>;
};
};
};
diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi
index cbebb6e4c616..4fc6676f5486 100644
--- a/arch/arm/boot/dts/uniphier-sld8.dtsi
+++ b/arch/arm/boot/dts/uniphier-sld8.dtsi
@@ -414,7 +414,8 @@
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
- resets = <&sys_rst 2>;
+ reset-names = "nand", "reg";
+ resets = <&sys_rst 2>, <&sys_rst 2>;
};
};
};
diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
index 48086c5e8549..e500911ce0a5 100644
--- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
+++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
@@ -323,11 +323,6 @@
};
&i2c0 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- status = "okay";
-
gpio5: io-expander@20 {
compatible = "nxp,pca9554";
reg = <0x20>;
@@ -350,11 +345,6 @@
};
&i2c2 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-
tca9548@70 {
compatible = "nxp,pca9548";
pinctrl-0 = <&pinctrl_i2c_mux_reset>;
diff --git a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts
index d7caf618f980..b642520199ba 100644
--- a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts
+++ b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts
@@ -407,7 +407,7 @@
pinctrl-0 = <&pinctrl_dspi1>;
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@@ -420,7 +420,7 @@
};
};
- spi-flash@1 {
+ flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@@ -509,7 +509,7 @@
#gpio-cells = <2>;
};
- lm75@48 {
+ temp-sensor@48 {
compatible = "national,lm75";
reg = <0x48>;
};
@@ -524,7 +524,7 @@
reg = <0x52>;
};
- ds1682@6b {
+ elapsed-time-recorder@6b {
compatible = "dallas,ds1682";
reg = <0x6b>;
};
@@ -536,7 +536,12 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
- adt7411@4a {
+ watchdog@38 {
+ compatible = "zii,rave-wdt";
+ reg = <0x38>;
+ };
+
+ adc@4a {
compatible = "adi,adt7411";
reg = <0x4a>;
};
@@ -548,7 +553,7 @@
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
- gpio9: sx1503q@20 {
+ gpio9: io-expander@20 {
compatible = "semtech,sx1503q";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sx1503_20>;
@@ -559,12 +564,12 @@
interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
};
- lm75@4e {
+ temp-sensor@4e {
compatible = "national,lm75";
reg = <0x4e>;
};
- lm75@4f {
+ temp-sensor@4f {
compatible = "national,lm75";
reg = <0x4f>;
};
@@ -576,17 +581,17 @@
reg = <0x23>;
};
- adt7411@4a {
+ adc@4a {
compatible = "adi,adt7411";
reg = <0x4a>;
};
- at24c08@54 {
+ eeprom@54 {
compatible = "atmel,24c08";
reg = <0x54>;
};
- tca9548@70 {
+ i2c-mux@70 {
compatible = "nxp,pca9548";
pinctrl-names = "default";
#address-cells = <1>;
@@ -625,7 +630,7 @@
};
};
- tca9548@71 {
+ i2c-mux@71 {
compatible = "nxp,pca9548";
pinctrl-names = "default";
reg = <0x71>;
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index ca6425ad794c..db3899b07992 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -59,6 +59,39 @@
regulator-always-on;
};
+ replicator {
+ compatible = "arm,coresight-static-replicator";
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* replicator output ports */
+ port@0 {
+ reg = <0>;
+ replicator_out_port0: endpoint {
+ remote-endpoint = <&tpiu_in_port>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ replicator_out_port1: endpoint {
+ remote-endpoint = <&etb_in_port>;
+ };
+ };
+ };
+ in-ports {
+ /* replicator input port */
+ port {
+ replicator_in_port0: endpoint {
+ remote-endpoint = <&funnel_out_port>;
+ };
+ };
+ };
+ };
+
amba: amba {
compatible = "simple-bus";
#address-cells = <1>;
@@ -365,5 +398,107 @@
reg = <0xf8005000 0x1000>;
timeout-sec = <10>;
};
+
+ etb@f8801000 {
+ compatible = "arm,coresight-etb10", "arm,primecell";
+ reg = <0xf8801000 0x1000>;
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+ in-ports {
+ port {
+ etb_in_port: endpoint {
+ remote-endpoint = <&replicator_out_port1>;
+ };
+ };
+ };
+ };
+
+ tpiu@f8803000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0xf8803000 0x1000>;
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+ in-ports {
+ port {
+ tpiu_in_port: endpoint {
+ remote-endpoint = <&replicator_out_port0>;
+ };
+ };
+ };
+ };
+
+ funnel@f8804000 {
+ compatible = "arm,coresight-static-funnel", "arm,primecell";
+ reg = <0xf8804000 0x1000>;
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+ /* funnel output ports */
+ out-ports {
+ port {
+ funnel_out_port: endpoint {
+ remote-endpoint =
+ <&replicator_in_port0>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* funnel input ports */
+ port@0 {
+ reg = <0>;
+ funnel0_in_port0: endpoint {
+ remote-endpoint = <&ptm0_out_port>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel0_in_port1: endpoint {
+ remote-endpoint = <&ptm1_out_port>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ funnel0_in_port2: endpoint {
+ };
+ };
+ /* The other input ports are not connect to anything */
+ };
+ };
+
+ ptm@f889c000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0xf889c000 0x1000>;
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+ cpu = <&cpu0>;
+ out-ports {
+ port {
+ ptm0_out_port: endpoint {
+ remote-endpoint = <&funnel0_in_port0>;
+ };
+ };
+ };
+ };
+
+ ptm@f889d000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0xf889d000 0x1000>;
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+ cpu = <&cpu1>;
+ out-ports {
+ port {
+ ptm1_out_port: endpoint {
+ remote-endpoint = <&funnel0_in_port1>;
+ };
+ };
+ };
+ };
};
};