aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/include/asm/memory.h
diff options
context:
space:
mode:
authorAndiii <andi.shyti@samsung.com>2016-01-14 07:17:00 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2016-01-26 23:49:02 +0000
commit9023cc8268c6ba358417d31112ed96e1feb73e56 (patch)
tree9c795d82edbb5716350055fa68a8e3c6556c329f /arch/arm/include/asm/memory.h
parentARM: 8497/1: initialize cpu_scale to its default (diff)
downloadlinux-dev-9023cc8268c6ba358417d31112ed96e1feb73e56.tar.xz
linux-dev-9023cc8268c6ba358417d31112ed96e1feb73e56.zip
ARM: 8499/1: irq: l2c: do not print error in case of missing l2c from
arm: irq: l2c: do not print error in case of missing l2c from dtb In some architectures the L2 cache controller is integrated in the processor's block itself and it doesn't use any external cache controller. This means that an entry in the board's dtb related to the l2c is not necessary. Distinguish between error codes and do not print anything in case l2x0_of_init() doesn't find any L2C DTB entry and returns -ENODEV. This patch mutes the following error message: L2C: failed to init: -19 on boards like odroid-xu4, cortex A7/A15, which don't have external cache controller. Signed-off-by: Andi Shyti <andi.shyti@samsung.com> Reported-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Tested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/include/asm/memory.h')
0 files changed, 0 insertions, 0 deletions