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| author |   Kukjin Kim <kgene.kim@samsung.com> | 2013-12-19 04:17:06 +0900 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2013-12-19 05:21:16 +0900 |
| commit | 7d8f159188410557630a7270efe3e14a1a305c2e (patch) | |
| tree | 85da5cca3bd055d5864ce35ce76be7666e7e7de1 /arch/arm/mach-exynos/include/mach/regs-clock.h | |
| parent | ARM: EXYNOS: cleanup <mach/regs-clock.h> (diff) | |
| download | linux-dev-7d8f159188410557630a7270efe3e14a1a305c2e.tar.xz linux-dev-7d8f159188410557630a7270efe3e14a1a305c2e.zip | |
PM / devfreq: move definitions for exynos4_bus into drivers/devfreq
We don't need to keep the definitions for exynos4_bus into
mach-exynos/ so this moves them into drviers/devfreq with
adding header file.
Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos/include/mach/regs-clock.h')
| -rw-r--r-- | arch/arm/mach-exynos/include/mach/regs-clock.h | 94 |
1 files changed, 0 insertions, 94 deletions
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h index d36a6a283b84..855f1b2c1fdc 100644 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h @@ -18,12 +18,6 @@ #define EXYNOS_CLKREG(x) (S5P_VA_CMU + (x)) -#define EXYNOS4_CLKDIV_LEFTBUS EXYNOS_CLKREG(0x04500) -#define EXYNOS4_CLKDIV_STAT_LEFTBUS EXYNOS_CLKREG(0x04600) - -#define EXYNOS4_CLKDIV_RIGHTBUS EXYNOS_CLKREG(0x08500) -#define EXYNOS4_CLKDIV_STAT_RIGHTBUS EXYNOS_CLKREG(0x08600) - #define EXYNOS4_EPLL_LOCK EXYNOS_CLKREG(0x0C010) #define EXYNOS4_VPLL_LOCK EXYNOS_CLKREG(0x0C020) @@ -41,24 +35,7 @@ #define EXYNOS4_CLKSRC_MASK_PERIL0 EXYNOS_CLKREG(0x0C350) #define EXYNOS4_CLKSRC_MASK_PERIL1 EXYNOS_CLKREG(0x0C354) -#define EXYNOS4_CLKDIV_TOP EXYNOS_CLKREG(0x0C510) -#define EXYNOS4_CLKDIV_CAM EXYNOS_CLKREG(0x0C520) -#define EXYNOS4_CLKDIV_MFC EXYNOS_CLKREG(0x0C528) - -#define EXYNOS4_CLKDIV_STAT_TOP EXYNOS_CLKREG(0x0C610) -#define EXYNOS4_CLKDIV_STAT_MFC EXYNOS_CLKREG(0x0C628) - -#define EXYNOS4210_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x0C930) -#define EXYNOS4212_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x04930) - #define EXYNOS4_CLKSRC_MASK_DMC EXYNOS_CLKREG(0x10300) -#define EXYNOS4_CLKDIV_DMC0 EXYNOS_CLKREG(0x10500) -#define EXYNOS4_CLKDIV_DMC1 EXYNOS_CLKREG(0x10504) -#define EXYNOS4_CLKDIV_STAT_DMC0 EXYNOS_CLKREG(0x10600) -#define EXYNOS4_CLKDIV_STAT_DMC1 EXYNOS_CLKREG(0x10604) - -#define EXYNOS4_DMC_PAUSE_CTRL EXYNOS_CLKREG(0x11094) -#define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0) #define EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200) #define EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400) @@ -74,81 +51,10 @@ #define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16) #define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0) -#define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4) -#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8) -#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12) -#define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16) -#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20) -#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24) -#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28) -#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT) - -#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0) -#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT) -#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4) -#define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT) -#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8) -#define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT) -#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12) -#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT) -#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16) -#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT) -#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24) -#define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT) - -#define EXYNOS4_CLKDIV_MFC_SHIFT (0) -#define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT) - -#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0) -#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT) -#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4) -#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) -#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8) -#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) -#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12) -#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) -#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16) -#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT) -#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20) -#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT) -#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24) -#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT) - -#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0) -#define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) -#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4) -#define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT) - -#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0) -#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT) -#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4) -#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT) -#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8) -#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT) -#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12) -#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT) - /* Only for EXYNOS4210 */ #define EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338) -/* Only for EXYNOS4212 */ - -#define EXYNOS4_CLKDIV_CAM1 EXYNOS_CLKREG(0x0C568) - -#define EXYNOS4_CLKDIV_STAT_CAM1 EXYNOS_CLKREG(0x0C668) - -#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0) -#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT) - /* For EXYNOS5250 */ #define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000) |