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| author |   Rajendra Nayak <rnayak@ti.com> | 2009-12-08 18:47:16 -0700 |
|---|---|---|
| committer |   paul <paul@twilight.(none)> | 2009-12-11 17:00:46 -0700 |
| commit | 16975a79c8e6ee424331f52649f2351d33c7b972 (patch) | |
| tree | 4efc6d4329e467b7c12a8838f544d6cfe928735e /arch/arm/mach-omap2/dpll.c | |
| parent | ARM: OMAP4: PM: Move DPLL control apis to dpll.c (diff) | |
| download | linux-dev-16975a79c8e6ee424331f52649f2351d33c7b972.tar.xz linux-dev-16975a79c8e6ee424331f52649f2351d33c7b972.zip | |
ARM: OMAP4: PM: Add support for OMAP4 dpll api's
Most of the dpll api's from dpll.c are reused for OMAP4.
This patch does extend a few api's for OMAP4 support.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Diffstat (limited to '')
| -rw-r--r-- | arch/arm/mach-omap2/dpll.c | 28 |
1 files changed, 17 insertions, 11 deletions
diff --git a/arch/arm/mach-omap2/dpll.c b/arch/arm/mach-omap2/dpll.c index a39fe9d8c278..f6055b493294 100644 --- a/arch/arm/mach-omap2/dpll.c +++ b/arch/arm/mach-omap2/dpll.c @@ -26,9 +26,9 @@ #include <linux/limits.h> #include <linux/bitops.h> -#include <mach/cpu.h> -#include <mach/clock.h> -#include <mach/sram.h> +#include <plat/cpu.h> +#include <plat/clock.h> +#include <plat/sram.h> #include <asm/div64.h> #include <asm/clkdev.h> @@ -311,10 +311,12 @@ int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) _omap3_noncore_dpll_bypass(clk); /* Set jitter correction */ - v = __raw_readl(dd->control_reg); - v &= ~dd->freqsel_mask; - v |= freqsel << __ffs(dd->freqsel_mask); - __raw_writel(v, dd->control_reg); + if (!cpu_is_omap44xx()) { + v = __raw_readl(dd->control_reg); + v &= ~dd->freqsel_mask; + v |= freqsel << __ffs(dd->freqsel_mask); + __raw_writel(v, dd->control_reg); + } /* Set DPLL multiplier, divider */ v = __raw_readl(dd->mult_div1_reg); @@ -346,7 +348,7 @@ int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) { struct clk *new_parent = NULL; - u16 freqsel; + u16 freqsel = 0; struct dpll_data *dd; int ret; @@ -382,9 +384,13 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) if (dd->last_rounded_rate == 0) return -EINVAL; - freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); - if (!freqsel) - WARN_ON(1); + /* No freqsel on OMAP4 */ + if (!cpu_is_omap44xx()) { + freqsel = _omap3_dpll_compute_freqsel(clk, + dd->last_rounded_n); + if (!freqsel) + WARN_ON(1); + } pr_debug("clock: %s: set rate: locking rate to %lu.\n", clk->name, rate); |