|author||Laura Abbott <firstname.lastname@example.org>||2015-01-21 17:36:06 -0800|
|committer||Catalin Marinas <email@example.com>||2015-01-22 14:54:29 +0000|
|parent||arm64: use fixmap for text patching (diff)|
arm64: add better page protections to arm64
Add page protections for arm64 similar to those in arm. This is for security reasons to prevent certain classes of exploits. The current method: - Map all memory as either RWX or RW. We round to the nearest section to avoid creating page tables before everything is mapped - Once everything is mapped, if either end of the RWX section should not be X, we split the PMD and remap as necessary - When initmem is to be freed, we change the permissions back to RW (using stop machine if necessary to flush the TLB) - If CONFIG_DEBUG_RODATA is set, the read only sections are set read only. Acked-by: Ard Biesheuvel <firstname.lastname@example.org> Tested-by: Kees Cook <email@example.com> Tested-by: Ard Biesheuvel <firstname.lastname@example.org> Signed-off-by: Laura Abbott <email@example.com> Signed-off-by: Catalin Marinas <firstname.lastname@example.org>
Diffstat (limited to 'arch/arm64/Kconfig.debug')
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm64/Kconfig.debug b/arch/arm64/Kconfig.debug
index 5fdd6dce8061..4a8741073c90 100644
@@ -66,4 +66,27 @@ config DEBUG_SET_MODULE_RONX
against certain classes of kernel exploits.
If in doubt, say "N".
+ bool "Make kernel text and rodata read-only"
+ If this is set, kernel text and rodata will be made read-only. This
+ is to help catch accidental or malicious attempts to change the
+ kernel's executable code. Additionally splits rodata from kernel
+ text so it can be made explicitly non-executable.
+ If in doubt, say Y
+ depends on DEBUG_RODATA && !ARM64_64K_PAGES
+ bool "Align linker sections up to SECTION_SIZE"
+ If this option is enabled, sections that may potentially be marked as
+ read only or non-executable will be aligned up to the section size of
+ the kernel. This prevents sections from being split into pages and
+ avoids a potential TLB penalty. The downside is an increase in
+ alignment and potentially wasted space. Turn on this option if
+ performance is more important than memory pressure.
+ If in doubt, say N