|author||Christopher Covington <firstname.lastname@example.org>||2017-01-31 12:50:19 -0500|
|committer||Will Deacon <email@example.com>||2017-02-01 15:41:50 +0000|
|parent||arm64: Improve detection of user/non-user mappings in set_pte(_at) (diff)|
arm64: Work around Falkor erratum 1009
During a TLB invalidate sequence targeting the inner shareable domain, Falkor may prematurely complete the DSB before all loads and stores using the old translation are observed. Instruction fetches are not subject to the conditions of this erratum. If the original code sequence includes multiple TLB invalidate instructions followed by a single DSB, onle one of the TLB instructions needs to be repeated to work around this erratum. While the erratum only applies to cases in which the TLBI specifies the inner-shareable domain (*IS form of TLBI) and the DSB is ISH form or stronger (OSH, SYS), this changes applies the workaround overabundantly-- to local TLBI, DSB NSH sequences as well--for simplicity. Based on work by Shanker Donthineni <firstname.lastname@example.org> Signed-off-by: Christopher Covington <email@example.com> Acked-by: Mark Rutland <firstname.lastname@example.org> Signed-off-by: Will Deacon <email@example.com>
Diffstat (limited to 'arch/arm64/Kconfig')
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index bac0d1bb58b5..0ce23130cc9b 100644
@@ -480,6 +480,16 @@ config CAVIUM_ERRATUM_27456
If unsure, say Y.
+ bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
+ default y
+ On Falkor v1, the CPU may prematurely complete a DSB following a
+ TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
+ one more time to fix the issue.
+ If unsure, say Y.