|author||Mark Brown <email@example.com>||2014-03-04 07:51:17 +0000|
|committer||Catalin Marinas <firstname.lastname@example.org>||2014-03-04 10:30:07 +0000|
|parent||arm64: advertise ARMv8 extensions to 32-bit compat ELF binaries (diff)|
arm64: topology: Implement basic CPU topology support
Add basic CPU topology support to arm64, based on the existing pre-v8 code and some work done by Mark Hambleton. This patch does not implement any topology discovery support since that should be based on information from firmware, it merely implements the scaffolding for integration of topology support in the architecture. No locking of the topology data is done since it is only modified during CPU bringup with external serialisation from the SMP code. The goal is to separate the architecture hookup for providing topology information from the DT parsing in order to ease review and avoid blocking the architecture code (which will be built on by other work) with the DT code review by providing something simple and basic. Following patches will implement support for interpreting topology information from MPIDR and for parsing the DT topology bindings for ARM, similar patches will be needed for ACPI. Signed-off-by: Mark Brown <email@example.com> Acked-by: Mark Rutland <firstname.lastname@example.org> [email@example.com: removed CONFIG_CPU_TOPOLOGY, always on if SMP] Signed-off-by: Catalin Marinas <firstname.lastname@example.org>
Diffstat (limited to 'arch/arm64/Kconfig')
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index c2056ca04ae2..140cd1a9dc0c 100644
@@ -165,6 +165,22 @@ config SMP
If you don't know what to do here, say N.
+ bool "Multi-core scheduler support"
+ depends on SMP
+ Multi-core scheduler support improves the CPU scheduler's decision
+ making when dealing with multi-core CPU chips at a cost of slightly
+ increased overhead in some places. If unsure say N here.
+ bool "SMT scheduler support"
+ depends on SMP
+ Improves the CPU scheduler's decision making when dealing with
+ MultiThreading at a cost of slightly increased overhead in some
+ places. If unsure say N here.
int "Maximum number of CPUs (2-32)"
range 2 32