|author||Catalin Marinas <email@example.com>||2019-10-28 16:12:40 +0000|
|committer||Catalin Marinas <firstname.lastname@example.org>||2019-10-28 16:12:40 +0000|
|parent||Merge remote-tracking branch 'arm64/for-next/fixes' into for-next/core (diff)|
|parent||arm64: Silence clang warning on mismatched value/register sizes (diff)|
Merge branch 'for-next/neoverse-n1-stale-instr' into for-next/core
Neoverse-N1 cores with the 'COHERENT_ICACHE' feature may fetch stale instructions when software depends on prefetch-speculation-protection instead of explicit synchronization.  The workaround is to trap I-Cache maintenance and issue an inner-shareable TLBI. The affected cores have a Coherent I-Cache, so the I-Cache maintenance isn't necessary. The core tells user-space it can skip it with CTR_EL0.DIC. We also have to trap this register to hide the bit forcing DIC-aware user-space to perform the maintenance. To avoid trapping all cache-maintenance, this workaround depends on a firmware component that only traps I-cache maintenance from EL0 and performs the workaround. For user-space, the kernel's work is to trap CTR_EL0 to hide DIC, and produce a fake IminLine. EL3 traps the now-necessary I-Cache maintenance and performs the inner-shareable-TLBI that makes everything better.  https://developer.arm.com/docs/sden885747/latest/arm-neoverse-n1-mp050-software-developer-errata-notice * for-next/neoverse-n1-stale-instr: arm64: Silence clang warning on mismatched value/register sizes arm64: compat: Workaround Neoverse-N1 #1542419 for compat user-space arm64: Fake the IminLine size on systems affected by Neoverse-N1 #1542419 arm64: errata: Hide CTR_EL0.DIC on systems affected by Neoverse-N1 #1542419
Diffstat (limited to 'arch/arm64/Kconfig')
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 3f047afb982c..56647b995a2b 100644
@@ -558,6 +558,22 @@ config ARM64_ERRATUM_1463225
If unsure, say Y.
+ bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
+ default y
+ This option adds a workaround for ARM Neoverse-N1 erratum
+ Affected Neoverse-N1 cores could execute a stale instruction when
+ modified by another CPU. The workaround depends on a firmware
+ Workaround the issue by hiding the DIC feature from EL0. This
+ forces user-space to perform cache maintenance.
+ If unsure, say Y.
bool "Cavium erratum 22375, 24313"