path: root/arch/arm64/Kconfig
diff options
authorWill Deacon <will@kernel.org>2019-10-17 13:42:42 -0700
committerWill Deacon <will@kernel.org>2019-10-17 13:42:42 -0700
commit777d062e5bee0e3c0751cdcbce116a76ee2310ec (patch)
treec63aada7db4af337a1077d75d4ac1d021393d378 /arch/arm64/Kconfig
parentarm64: tags: Preserve tags for addresses translated via TTBR1 (diff)
parentarm64: Allow CAVIUM_TX2_ERRATUM_219 to be selected (diff)
Merge branch 'errata/tx2-219' into for-next/fixes
Workaround for Cavium/Marvell ThunderX2 erratum #219. * errata/tx2-219: arm64: Allow CAVIUM_TX2_ERRATUM_219 to be selected arm64: Avoid Cavium TX2 erratum 219 when switching TTBR arm64: Enable workaround for Cavium TX2 erratum 219 when running SMT arm64: KVM: Trap VM ops when ARM64_WORKAROUND_CAVIUM_TX2_219_TVM is set
Diffstat (limited to 'arch/arm64/Kconfig')
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 950a56b71ff0..3f047afb982c 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -616,6 +616,23 @@ config CAVIUM_ERRATUM_30115
If unsure, say Y.
+config CAVIUM_TX2_ERRATUM_219
+ bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
+ default y
+ help
+ On Cavium ThunderX2, a load, store or prefetch instruction between a
+ TTBR update and the corresponding context synchronizing operation can
+ cause a spurious Data Abort to be delivered to any hardware thread in
+ the CPU core.
+ Work around the issue by avoiding the problematic code sequence and
+ trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
+ trap handler performs the corresponding register access, skips the
+ instruction and ensures context synchronization by virtue of the
+ exception return.
+ If unsure, say Y.
bool "Falkor E1003: Incorrect translation due to ASID change"
default y