path: root/arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi
diff options
authorChris Packham <chris.packham@alliedtelesis.co.nz>2022-07-05 22:09:20 +0300
committerGregory CLEMENT <gregory.clement@bootlin.com>2022-07-19 15:12:43 +0200
commitb795fadfc46bc497257435d4d9e57f487f521fd1 (patch)
tree240a845edbfb0ea3f3bb50552560883019f440fc /arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi
parentdt-bindings: marvell: Document the AC5/AC5X compatibles (diff)
arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board
The 98DX2530 SoC is the Control and Management CPU integrated into the Marvell 98DX25xx and 98DX35xx series of switch chip (internally referred to as AlleyCat5 and AlleyCat5X). These files have been taken from the Marvell SDK and lightly cleaned up with the License and copyright retained. gregory.clement: use specific cpu type: cortex-a55 instead of armv8 in cpu nodes, armv8 being reserved for the arm virtual models that are not meant to implement a particular CPU type. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Vadym Kochan <vadym.kochan@plvision.eu> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to '')
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi
new file mode 100644
index 000000000000..2ab72f854bea
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ * Device Tree For AC5X.
+ *
+ * Copyright (C) 2022 Allied Telesis Labs
+ */
+#include "ac5-98dx25xx.dtsi"
+/ {
+ model = "Marvell AC5X SoC";
+ compatible = "marvell,ac5x", "marvell,ac5";
+&cnm_clock {
+ clock-frequency = <325000000>;