diff options
| author |   Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2022-06-20 10:19:34 +0300 |
|---|---|---|
| committer |   Bjorn Andersson <bjorn.andersson@linaro.org> | 2022-07-06 21:30:09 -0500 |
| commit | b874fff9a7683df30e5aff16d5a85b1f8a43aa5d (patch) | |
| tree | 8fc5d22e5a8839b103366de9f938d233ef703ce4 /arch/arm64/boot/dts/qcom/msm8996.dtsi | |
| parent | arm64: dts: qcom: sdm845-shift-axolotl: Enable pmi9889 LPG LED (diff) | |
| download | linux-dev-b874fff9a7683df30e5aff16d5a85b1f8a43aa5d.tar.xz linux-dev-b874fff9a7683df30e5aff16d5a85b1f8a43aa5d.zip | |
arm64: dts: qcom: msm8996: correct #clock-cells for QMP PHY nodes
The commit 82d61e19fccb ("arm64: dts: qcom: msm8996: Move '#clock-cells'
to QMP PHY child node") moved the '#clock-cells' properties to the child
nodes. However it missed the fact that the property must have been set
to <0> (as all pipe clocks use of_clk_hw_simple_get as the xlate
function. Also the mentioned commit didn't add '#clock-cells' properties
to second and third PCIe PHY nodes. Correct both these mistakes:
- Set '#clock-cells' to <0>,
- Add the property to pciephy_1 and pciephy_2 nodes.
Fixes: 82d61e19fccb ("arm64: dts: qcom: msm8996: Move '#clock-cells' to QMP PHY child node")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220620071936.1558906-3-dmitry.baryshkov@linaro.org
Diffstat (limited to '')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/msm8996.dtsi | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index b9a37e7a2ade..469a6bc88a63 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -610,7 +610,7 @@ <0x00035400 0x1dc>; #phy-cells = <0>; - #clock-cells = <1>; + #clock-cells = <0>; clock-output-names = "pcie_0_pipe_clk_src"; clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; clock-names = "pipe0"; @@ -624,6 +624,7 @@ <0x00036400 0x1dc>; #phy-cells = <0>; + #clock-cells = <0>; clock-output-names = "pcie_1_pipe_clk_src"; clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; clock-names = "pipe1"; @@ -637,6 +638,7 @@ <0x00037400 0x1dc>; #phy-cells = <0>; + #clock-cells = <0>; clock-output-names = "pcie_2_pipe_clk_src"; clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; clock-names = "pipe2"; @@ -2951,7 +2953,7 @@ <0x07410600 0x1a8>; #phy-cells = <0>; - #clock-cells = <1>; + #clock-cells = <0>; clock-output-names = "usb3_phy_pipe_clk_src"; clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; clock-names = "pipe0"; |