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author | 2022-07-10 11:41:28 +0300 | |
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committer | 2022-07-16 10:18:14 -0500 | |
commit | 0f1e23651a0ab71c82ab098ecbfc9ee7a4d74ced (patch) | |
tree | f4aa304682c90b190b45f9a69ce40adcb0ea4cdb /arch/arm64/boot/dts/qcom/sc7280.dtsi | |
parent | arm64: dts: qcom: sc7280: split register block for DP controller (diff) | |
download | linux-dev-0f1e23651a0ab71c82ab098ecbfc9ee7a4d74ced.tar.xz linux-dev-0f1e23651a0ab71c82ab098ecbfc9ee7a4d74ced.zip |
arm64: dts: qcom: sc7280: drop #clock-cells from displayport-controller
Drop #clock-cells from DP device node. It is a leftover from the times
before splitting the deviice into controller and PHY devices. Now the
clocks are provided by the PHY, while the controller doesn't provide any
clocks.
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220710084133.30976-5-dmitry.baryshkov@linaro.org
Diffstat (limited to '')
-rw-r--r-- | arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 3f8b50863ba7..02d5253b0167 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3730,7 +3730,6 @@ "ctrl_link", "ctrl_link_iface", "stream_pixel"; - #clock-cells = <1>; assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; @@ -3829,7 +3828,6 @@ "ctrl_link", "ctrl_link_iface", "stream_pixel"; - #clock-cells = <1>; assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; |