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| author |   Rajendra Nayak <rnayak@codeaurora.org> | 2020-09-01 19:50:25 +0530 |
|---|---|---|
| committer |   Bjorn Andersson <bjorn.andersson@linaro.org> | 2020-09-10 22:03:11 +0000 |
| commit | 137154871cf469af0e8def123511c37096583919 (patch) | |
| tree | 6009f18f9319737ff863676b567b2e8116bde610 /arch/arm64/boot/dts/qcom/sdm845.dtsi | |
| parent | arm64: dts: qcom: sc7180: add interconnect bindings for display (diff) | |
| download | linux-dev-137154871cf469af0e8def123511c37096583919.tar.xz linux-dev-137154871cf469af0e8def123511c37096583919.zip | |
arm64: dts: qcom: sdm845: Add OPP tables and power-domains for venus
Add the OPP tables in order to be able to vote on the performance state of
a power-domain.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1598970026-7199-5-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Diffstat (limited to '')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sdm845.dtsi | 40 |
1 files changed, 38 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 2884577dcb77..86457d9bc229 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3639,8 +3639,10 @@ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&videocc VENUS_GDSC>, <&videocc VCODEC0_GDSC>, - <&videocc VCODEC1_GDSC>; - power-domain-names = "venus", "vcodec0", "vcodec1"; + <&videocc VCODEC1_GDSC>, + <&rpmhpd SDM845_CX>; + power-domain-names = "venus", "vcodec0", "vcodec1", "cx"; + operating-points-v2 = <&venus_opp_table>; clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, <&videocc VIDEO_CC_VENUS_AHB_CLK>, <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, @@ -3662,6 +3664,40 @@ video-core1 { compatible = "venus-encoder"; }; + + venus_opp_table: venus-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-380000000 { + opp-hz = /bits/ 64 <380000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-444000000 { + opp-hz = /bits/ 64 <444000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-533000097 { + opp-hz = /bits/ 64 <533000097>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; }; videocc: clock-controller@ab00000 { |