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author | Kunihiko Hayashi <hayashi.kunihiko@socionext.com> | 2022-09-13 13:23:21 +0900 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2022-09-28 22:41:48 +0200 |
commit | 5381a96cd9c4247eafb2dfcfccf491d0bba2f5ca (patch) | |
tree | cb8a2a7545007dd2ae5a8dd80ab9d587daff3bcf /arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | |
parent | arm64: dts: uniphier: Remove compatible "snps,dw-pcie" from pcie node (diff) | |
download | linux-dev-5381a96cd9c4247eafb2dfcfccf491d0bba2f5ca.tar.xz linux-dev-5381a96cd9c4247eafb2dfcfccf491d0bba2f5ca.zip |
arm64: dts: uniphier: Add L2 cache node
Add a L2 cache node referenced from CPU nodes as the missing cache hierarchy
information because the following warning was issued.
cacheinfo: Unable to detect cache hierarchy for CPU 0
Early cacheinfo failed, ret = -2
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042321.4817-11-hayashi.kunihiko@socionext.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to '')
-rw-r--r-- | arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi index f10685625b6a..b0c29510a7da 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi @@ -43,6 +43,7 @@ reg = <0 0x000>; clocks = <&sys_clk 33>; enable-method = "psci"; + next-level-cache = <&l2>; operating-points-v2 = <&cluster0_opp>; #cooling-cells = <2>; }; @@ -53,6 +54,7 @@ reg = <0 0x001>; clocks = <&sys_clk 33>; enable-method = "psci"; + next-level-cache = <&l2>; operating-points-v2 = <&cluster0_opp>; #cooling-cells = <2>; }; @@ -63,6 +65,7 @@ reg = <0 0x002>; clocks = <&sys_clk 33>; enable-method = "psci"; + next-level-cache = <&l2>; operating-points-v2 = <&cluster0_opp>; #cooling-cells = <2>; }; @@ -73,9 +76,14 @@ reg = <0 0x003>; clocks = <&sys_clk 33>; enable-method = "psci"; + next-level-cache = <&l2>; operating-points-v2 = <&cluster0_opp>; #cooling-cells = <2>; }; + + l2: l2-cache { + compatible = "cache"; + }; }; cluster0_opp: opp-table { |